NXP Semiconductors PXN2020, Reference Manual, Page: 612 / 1376

Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
25-46 Freescale Semiconductor
Table 25-36. Receive Buffer Descriptor Field Definitions
Halfword Location Field Name Description
0 Bit 0 E Empty. Written by the FEC (=0) and user (=1).
0 The data buffer associated with this BD has been filled with received data, or data
reception has been aborted due to an error condition. The status and length fields
have been updated as required.
1 The data buffer associated with this BD is empty, or reception is currently in
progress.
0 Bit 1 RO1 Receive software ownership.
This field is reserved for use by software. This read/write bit is not modified by
hardware, and its value does not affect hardware.
0 Bit 2 W Wrap. Written by user.
0 The next buffer descriptor is found in the consecutive location
1 The next buffer descriptor is found at the location defined in ERDSR.
0 Bit 3 RO2 Receive software ownership.
This field is reserved for use by software. This read/write bit is not modified by
hardware, and its value does not affect hardware.
0 Bit 4 L Last in frame. Written by the FEC.
0 The buffer is not the last in a frame.
1 The buffer is the last in a frame.
0 Bits 5-6 — Reserved.
0 Bit 7 M Miss. Written by the FEC. This bit is set by the FEC for frames that were accepted in
promiscuous mode, but were flagged as a “miss” by the internal address recognition.
Thus, while in promiscuous mode, the user can use the M-bit to quickly determine
whether the frame was destined to this station. This bit is valid only if the L-bit is set
and the PROM bit is set.
0 The frame was received because of an address recognition hit.
1 The frame was received because of promiscuous mode.
0 Bit 8 BC Set if the DA is broadcast (FF-FF-FF-FF-FF-FF).
0 Bit 9 MC Set if the DA is multicast and not BC.
0 Bit 10 LG Rx frame length violation. Written by the FEC. A frame length greater than
RCR[MAX_FL] was recognized. This bit is valid only if the L-bit is set. The receive
data is not altered in any way unless the length exceeds 2047 bytes.
0 Bit 11 NO Receive non-octet aligned frame. Written by the FEC. A frame that contained a
number of bits not divisible by 8 was received, and the CRC check that occurred at
the preceding byte boundary generated an error. This bit is valid only if the L-bit is
set. When this bit is set, the CR bit will not be set.
0 Bit 12 — Reserved.
0 Bit 13 CR Receive CRC error. Written by the FEC. This frame contains a CRC error and is an
integral number of octets in length. This bit is valid only if the L-bit is set.
0 Bit 14 OV Overrun. Written by the FEC. A receive FIFO overrun occurred during frame
reception. If this bit is set, the other status bits, M, LG, NO, CR, and CL lose their
normal meaning and will be zero. This bit is valid only if the L-bit is set.
0 Bit 15 TR Set if the receive frame is truncated (frame length > 2047 bytes). If the TR bit is set
the frame should be discarded and the other error bits should be ignored as they may
be incorrect.