NXP Semiconductors PXN2020, Reference Manual, Page: 311 / 1376

Interrupts and Interrupt Controller (INTC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 10-43
timing diagram for this scenario, and Table 10-14 explains the events. The example is for software vector
mode, but except for the method of retrieving the vector and acknowledging the interrupt request to the
processor, hardware vector mode is identical.
Figure 10-22. Raised Priority Preserved Timing Diagram
Table 10-14. Raised Priority Preserved Events
Event Description
A Peripheral interrupt request 200 asserts during execution of ISR108 running at priority 1.
B Interrupt request to processor asserts. INTVEC in INTC_IACKR updates with vector for that peripheral interrupt
request.
C ISR108 writes to INTC_CPR to raise priority to 3 before accessing shared coherent data block.
D PRI in INTC_CPR now at 3, reflecting the write. This write, just before accessing data block, is the last instruction the
processor executes before being interrupted.
E Interrupt exception handler prolog acknowledges interrupt by reading INTC_IACKR.
F PRI of 3 pushed onto LIFO. PRI in INTC_CPR updates to 2, the priority of ISR208.
G ISR208 clears its flag bit, deasserting its peripheral interrupt request.
Last In / First Out
Entry in LIFO
Write
INTC_CPR
Clock
Interrupt Request
to Processor
Hardware Vector
Enable
Interrupt
Acknowledge
Interrupt Vector
Read
INTC_IACKR
Write
INTC_EOIR
INTVEC in
INTC_IACKR
PRI in
INTC_CPR
Peripheral Interrupt
Request 100
0
108
1
208
2 3
Peripheral Interrupt
Request 200
0 3 0
3
A
B
C
D
E
F
G
H
I