NXP Semiconductors PXN2020, Reference Manual, Page: 172 / 1376

Frequency Modulated Phase-Locked Loop (FMPLL)
PXN20 Microcontroller Reference Manual, Rev. 1
7-10 Freescale Semiconductor
7.4 Functional Description
The FMPLL module contains the frequency modulated phase lock loop (FMPLL), enhanced frequency
divider (ERFD), enhanced synthesizer control registers (ESYNCR1 and ESYNCR2), synthesizer status
register (SYNSR), and clock/PLL control logic. The block also contains a reference frequency pre-divider
controlled by the EPREDIV bits in the ESYNCR1. This enables the user to use a high frequency crystal
or external clock generator and obtain finer frequency synthesis resolution than would be available if the
raw input clock were used directly by the analog loop. For the remainder of this chapter, the term
“reference frequency” and the symbol F
ref
indicate the output of the pre-divider circuit. This is the clock
on which frequency multiplication is performed.
7.4.1 General
At reset, the system clock is driven by the internal oscillator (16 MHz IRC) and the module is in PLL Off
mode. After reset, software can change the PLL mode (see
Section 7.5.1, Clock Mode Selection ).
Table 7-11 shows the PLL-clock to input-clock frequency relationships for the available clock modes.
Table 7-10. Output Divide Ratios
ERFD Output Divide Ratio (ERFD+1)
00_0000 1
00_0001 2
00_0010 Invalid
00_0011 4 (default value for PXN20)
00_0100 Invalid
00_0101 6
00_0110 Invalid
00_0111 8
.
.
. .
.
.
11_1100 Invalid
11_1101 62
11_1110 Invalid
11_1111 64
Table 7-11. Clock-Out vs. Clock-In Relationships
Clock Mode Frequency Equation
Normal PLL Mode
F
sys
F
extal
EMFD 16 +
 

EPREDIV 1 +
 
ERFD 1 +
 
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