NXP Semiconductors PXN2020, Reference Manual, Page: 135 / 1376

Clocks, Reset, and Power (CRP)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 6-3
— Four selectable counter clock sources
– 4 – 40 MHz XTAL with 1 to 16 divider
– 32 kHz XTAL
– 16 MHz_IRC with 1 to 16 divider stage
– 128 kHz_IRC with 1 to 4 divider stage
— Optional divide-by-512 prescaler and optional divide-by-32 prescaler connected in series in the
clock path feeding the 32-bit counter
— 32-bit counter supports times up to greater than 1.5 months with 1 ms resolution.
— 12-bit compare value to support interrupt intervals of 1 s up to greater than 1 hr with 1 s
resolution
— RTC interrupt with interrupt enable.
— Counter runs in all modes of operation.
— RTC status and control register are reset only by POR
— RTC counter is reset when counter is disabled by software and by POR.
— Autonomous periodic interrupt support includes:
– 10-bit compare value to support wakeup intervals of 1.0 ms to 1 s
– Wakeup logic has separate enable to support changing compare value while RTC running
– API interrupt with interrupt enable
– Operates in all modes of operation
– API compare value can be modified while RTC is running
— Optional interrupt for RTC match, API match, and RTC rollover.
• Low-power mode management:
— Provides control of voltage regulator, LVI circuits, isolation enables, and power switches
— FSM clock gates itself off when waiting for asynchronous wakeup signal for power savings
— Four selections available for block sizes for RAM data retention (0, 32 KB, 64 KB, and
128 KB)
• Low-power wakeup:
— Wakeup sources can be either the RTC, API, RTC rollover, or external pin
— All wakeup sources can be enabled at any given time (first to occur generates wakeup)
— 32 pin wakeup sources
— Pin wakeup occurs on rising edge, falling edge, or both
— Two clock-source inputs for pin wakeup to allow for lower power or faster wakeup
— System level reset control to ensure clean recovery from sleep mode
• Miscellaneous:
— All functional logic inputs isolated in low-power modes
— All logic with multiple clock sources internally synchronized