NXP Semiconductors PXN2020, Reference Manual, Page: 794 / 1376

Media Local Bus (MLB)
PXN20 Microcontroller Reference Manual, Rev. 1
27-22 Freescale Semiconductor
NOTE
If the MLB DMA attempts to write to an invalid memory address, then the
Host Bus Error bit of Channel N Status Configuration Register
(CSCRn[HBE]) is not set as expected. CSCRn[HBE] will be set correctly if
MLB DMA attempts to read from an invalid memory address. Therefore,
ensure MLB DMA writes are to valid memory addresses.
27.3.2.13 Channel n Current Buffer Configuration Register
The Channel n Current Buffer Configuration Register (CCBCR n ) allows system software to monitor the
address pointer and buffer length of the Current Buffer in system memory for the logical channel. The
definitions of the bit fields in the CCBCR n register vary depending on the selected channel type.
BE Buffer Error. When set, this bit indicates that either a TX channel has detected a buffer underflow (e.g. attempted to
pop data from an empty buffer), or an RX channel has detected a buffer overflow (e.g. attempted to push data onto
a full buffer). The setting of this bit generates a maskable channel interrupt to system software. This bit is valid for
synchronous RX/TX and isochronous RX (CECRn[FCE] = 0) channels only.
0 TX underflow or RX overflow not detected.
1 TX underflow or RX overflow detected.
CBS Current Buffer Start. When set, this bit indicates the first quadlet of the Current Buffer has been successfully
transmitted or received. The setting of this bit generates a maskable channel interrupt to system software. This bit
is valid for all channel types.
0 First quadlet of the Current Buffer has not been successfully transmitted or received.
1 First quadlet of the Current Buffer has been successfully transmitted or received.
CBD Current Buffer Done. When set, this bit indicates the last quadlet of the Current Buffer has been successfully
transmitted or received. The setting of this bit generates a maskable channel interrupt to system software. This bit
is valid for all channel types. The Done status is always generated when the processing of a buffer has finished, even
if a Break or Error condition was detected during the packet processing. If Break or Error occurred, the Done status
bit is set in addition to the Break or Error status bit.
0 Last quadlet of the Current Buffer has not been successfully transmitted or received.
1 Last quadlet of the Current Buffer has been successfully transmitted or received.
CBDB Current Buffer Detect Break. When set, this bit indicates that either a TX channel has detected a receiver break
response, ReceiverBreak (70h), or an RX channel has detected a transmitter break command, ControlBreak (36h)
or AsyncBreak (26h), while processing the Current Buffer. The setting of this bit generates a maskable channel
interrupt to system software. This bit is valid for all channel types.
0 Break response was not detected while processing the Current Buffer.
1 Break response was detected while processing the Current Buffer.
CBPE Current Buffer Protocol Error. When set, this bit indicates that either a TX channel has detected an RxStatus of
ReceiverProtocolError (72h), a RX channel has detected an invalid command for this channel type, or an additional
AsyncStart (20h) or ControlStart (30h) command has been received while in the middle of a packet. The setting of
this bit generates a maskable channel interrupt to system software. This bit is valid for all RX channels and valid for
only asynchronous and control TX channels.
0 Protocol error was not detected while processing the Current Buffer.
1 Protocol error was detected while processing the Current Buffer.
Table 27-19. Channel n Status Configuration Register Field Descriptions (continued)
Field Description