NXP Semiconductors PXN2020, Reference Manual, Page: 351 / 1376

Flash Memory Array and Control
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 12-25
12.3.2.13 User Test Register 1 (UT1)
The User Test Register 1 (UT1) provides added controllability to UTest.
AIS Array Integrity Sequence. AIS determines the address sequence to be used during array integrity checks. The
default sequence (AIS = 0) is meant to replicate sequences normal “user” code follows, and thoroughly checks
the read propagation paths. This sequence is proprietary. The alternative sequence (AIS = 1) is just logically
sequential.
It should be noted that the time to run a sequential sequence is significantly shorter than the time to run the
proprietary sequence. If MRE is set, AIS has no effect.
0 Array integrity sequence is proprietary sequence.
1 Array integrity sequence is sequential.
AIE Array Integrity Enable. AIE set to one starts the array integrity check done on all selected and unlocked blocks.
The address sequence selected is determined by AIS, and the MISR (UM0 through UM4) can be checked after
the operation is complete, to determine if a correct signature is obtained. Once an Array Integrity operation is
requested (AIE = 1), it may be terminated by clearing AIE if the operation has finished (AID = 1) or aborted by
clearing AIE if the operation is ongoing (AID = 0). AIE is not simultaneously writable to a 1 as UTI is being cleared
to a 0.
0 Array integrity checks are not enabled.
1 Array integrity checks are enabled.
AID Array Integrity Done. AID is cleared upon an Array integrity check being enabled (to signify the operation is
ongoing). Once completed, AID is set to indicate that the array integrity check is complete. At this time the MISR
(UMR registers) can be checked. AID can not be written, and is status only.
0 Array integrity check is ongoing.
1 Array integrity check is done.
Offset: FLASH_REG 0x0040 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DAI
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
DAI
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 12-15. User Test Register 1 (UT1)
Table 12-17. UT1 Field Descriptions
Field Description
DAI
[31:0]
Data Array Input. These bits enable checks of ECC logic by allowing data bits to be input into the ECC logic
and then read out by doing array reads or array integrity checks. The DAI[31:0] correspond to the 32 Array bits
representing Word 0 of the double word selected in the ADR register.
Table 12-16. UT0 Field Descriptions (continued)
Field Description