NXP Semiconductors PXN2020, Reference Manual, Page: 695 / 1376

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-81
26.6.3.2 Receive Shadow Buffers
The receive shadow buffers are required for the frame reception process for individual message buffers.
The controller provides four receive shadow buffers, one receive shadow buffer per channel and per
message buffer segment.
Each receive shadow buffer consists of two parts, the physical message buffer located in the FlexRay
memory and the receive shadow buffer control registers located in dedicated registers. The structure of a
receive shadow buffer is shown in
Figure 26-105 . The four internal shadow buffer control registers can be
accessed by the Receive Shadow Buffer Index Register (RSBIR) .
The connection between the receive shadow buffer control register and the physical message buffer for the
selected receive shadow buffer is established by the receive shadow buffer index field RSBIDX in the
Receive Shadow Buffer Index Register (RSBIR) . The start address SADR_MBHF of the related message
buffer header field in the FlexRay memory is determined according to Equation 26-4 .
SADR_MBHF = (RSBIR[RSBIDX] * 10) + SMBA Eqn. 26-4
The length required for the message buffer data field depends on the message buffer segment that the
receive shadow buffer is assigned to. For the receive shadow buffers assigned to the first message buffer
segment, the length must be the same as for the individual message buffers assigned to the first message
buffer segment. For the receive shadow buffers assigned to the second message buffer segment, the length
must be the same as for the individual message buffers assigned to the second message buffer segment.
The receive shadow buffer assignment is described in
Receive Shadow Buffer Index Register (RSBIR) .
Figure 26-105. Receive Shadow Buffer Structure
26.6.3.3 Receive FIFO
The receive FIFO implements a frame reception system based on the FIFO concept. The controller
provides two independent receive FIFOs, one per channel.
RSBIDX[3]
RSBIDX[2]
RSBIDX[1]
RSBIDX[0]
Receive Shadow Buffer Control Register
(min) MBDSR[MBSEG1DS] * 2 bytes / MBDSR[MBSEG2DS] * 2 bytes
Data Field Offset
Frame Data
Message Buffer Header Field
Message Buffer Data Field
Slot Status Frame Header
SADR_MBDF
SADR_MBHF
Fle
x
Ra
y Memor
y