NXP Semiconductors PXN2020, Reference Manual, Page: 937 / 1376

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 30-11
In continuous clock mode, only t
DT
is supported for TSB. However, in TSB noncontinuous clock mode,
both the PDT and DT delays are valid.
.
Offset: DSP 0x000C (DSPI_CTAR0)
0x0010 (DSPI_CTAR1)
0x0014 (DSPI_CTAR2)
0x0018 (DSPI_CTAR3)
0x001C (DSPI_CTAR4)
0x0020 (DSPI_CTAR5)
0x0024 (DSPI_CTAR6)
0x0028 (DSPI_CTAR7) Access: User
read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DBR FMSZ CPOL CPHA
LSB
FE
PCSSCK PASC PDT PBR
W
Reset 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CSSCK ASC DT BR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 30-5. DSPI Clock and Transfer Attributes Registers 0–7 (DSPI_CTARn)
Table 30-5. DSPI_CTARn Field Description
Field Description
DBR Double Baud Rate. The DBR bit doubles the effective baud rate of the Serial Communications Clock (SCK). This
field is only used in master mode. It effectively halves the baud rate division ratio supporting faster frequencies
and odd division ratios for the serial communications clock (SCK). When the DBR bit is set, the duty cycle of the
SCK depends on the value in the baud rate prescaler and the clock phase bit as listed in
Table 30-6 . See the
BR[0:3] field description for details on how to compute the baud rate. If the overall baud rate is divide by two or
divide by three of the system clock then neither the continuous SCK enable or the modified timing format enable
bits should be set.
0 The baud rate is computed normally with a 50/50 duty cycle.
1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.
FMSZ Frame Size. The FMSZ field selects the number of bits transferred per frame. The FMSZ field is used in Master
Mode and Slave Mode.
Table 30-7 lists the frame size encodings.
When operating in TSB confirmation, detailed on Section 30.4.10, Timed Serial Bus (TSB), the FMSZ defines
the point with in the 32-bit (maximum length) frame where control of the CS switches from the DSPI_DSICR to
the DSPI_DSICR1 register. The cross over point must range between 4 bits and 16 bits and is encoded per
Table 30-7 . The remaining frame after the cross over point, regardless of how many bits are remaining, is
controlled by the DSPI_DSICR1 register.
CPOL Clock Polarity. The CPOL bit selects the inactive state of the Serial Communications Clock (SCK). This bit is used
in both Master and Slave Mode. For successful communication between serial devices, the devices must have
identical clock polarities. When the Continuous Selection Format is selected, switching between clock polarities
without stopping the DSPI can cause errors in the transfer due to the peripheral device interpreting the switch of
clock polarity as a valid clock edge.
0 The inactive state value of SCK is low.
1 The inactive state value of SCK is high.