NXP Semiconductors PXN2020, Reference Manual, Page: 1084 / 1376

Analog-to-Digital Converter (ADC)
PXN20 Microcontroller Reference Manual, Rev. 1
34-4 Freescale Semiconductor
0x006C THRHLR3 — Threshold Register 3 R/W
1
0x0FFF_0000 34.3.2.18/34-21 32
0x0070–0x007C Reserved
0x0080 PSCR — Presampling Control Register R/W
1
0x0000_0000 34.3.2.19/34-22 32
0x0084 PSR0 — Presampling Register 0 R/W
1
0x0000_0000 34.3.2.20/34-22 32
0x0088 PSR1 — Presampling Register 1 R/W
1
0x0000_0000 34.3.2.21/34-23 32
0x008C PSR2 — Presampling Register 2 R/W
1
0x0000_0000 34.3.2.22/34-23 32
0x0090 Reserved
0x0094 CTR0 — Conversion Timing Register 0 R/W
1
0x0000_0203 34.3.2.23/34-24 32
0x0098 CTR1— Conversion Timing Register 1 R/W
1
0x0000_0203 34.3.2.24/34-24 32
0x009C CTR2 — Conversion Timing Register 2 R/W
1
0x0000_0203 34.3.2.25/34-25 32
0x00A0 Reserved
0x00A4 NCMR0 — Normal Conversion Mask Register 0 R/W
1
0x0000_0000 34.3.2.26/34-33 32
0x00A8 NCMR1 — Normal Conversion Mask Register 1 R/W
1
0x0000_0000 34.3.2.27/34-34 32
0x00AC NCMR2 — Normal Conversion Mask Register 2 R/W
1
0x0000_0000 34.3.2.28/34-34 32
0x00B0 Reserved
0x00B4 JCMR0 — Injected Conversion Mask Register 0 R/W
1
0x0000_0000 34.3.2.29/34-35 32
0x00B8 JCMR1 — Injected Conversion Mask Register 1 R/W
1
0x0000_0000 34.3.2.30/34-35 32
0x00BC JCMR2 — Injected Conversion Mask Register 2 R/W
1
0x0000_0000 34.3.2.31/34-36 32
0x00C0 OFFWR — Offset Word Register R/W
1
0x0000_0000 34.3.2.32/34-36 32
0x00C4 DSDR — Decode Signals Delay Register R/W
1
0x0000_0000 34.3.2.33/34-37 32
0x00C8 PDEDR — Power Down Exit Delay Register R/W
1
0x0000_0000 34.3.2.34/34-38 32
0x00CC – 0x00FC Reserved
0x0100 PRECDATAREG0 — Channel 0 Data Register RO 0x0000_0000 34.3.2.35/34-38 32
0x0104 PRECDATAREG1 — Channel 1 Data Register RO 0x0000_0000 34.3.2.35/34-38 32
0x0108 PRECDATAREG2 — Channel 2 Data Register RO 0x0000_0000 34.3.2.35/34-38 32
0x010C PRECDATAREG3 — Channel 3 Data Register RO 0x0000_0000 34.3.2.35/34-38 32
0x0110 PRECDATAREG4 — Channel 4 Data Register RO 0x0000_0000 34.3.2.35/34-38 32
0x0114 PRECDATAREG5 — Channel 5 Data Register RO 0x0000_0000 34.3.2.35/34-38 32
0x0118 PRECDATAREG6 — Channel 6 Data Register RO 0x0000_0000 34.3.2.35/34-38 32
0x011C PRECDATAREG7 — Channel 7 Data Register RO 0x0000_0000 34.3.2.35/34-38 32
0x0120 PRECDATAREG8 — Channel 8 Data Register RO 0x0000_0000 34.3.2.35/34-38 32
Table 34-1. ADC Memory Map (continued)
Offset from
ADC_BASE
(ADC_A=
0xFFF8_0000)
Register Access Reset Value Section/Page Size