NXP Semiconductors PXN2020, Reference Manual, Page: 1191 / 1376

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 36-41
36.6.8.8 Data Trace Start Address Registers 1 and 2 (DTSAn)
The data trace start address registers define the start addresses for each trace channel.
36.6.8.9 Data Trace End Address Registers 1 and 2 (DTEAn)
The data trace end address registers define the end addresses for each trace channel.
Table 36-28. DTC Field Description
Field Description
31–30
RWT1[1:0]
Read/write trace 1.
00 No trace enabled.
x1 Enable data read trace.
1x Enable data write trace.
29–28
RWT2[1:0]
Read/write trace 2.
00 No trace enabled.
x1 Enable data read trace.
1x Enable data write trace.
7
RC1
Range control 1.
0 Condition trace on address within range.
1 Condition trace on address outside of range.
6
RC2
Range control 2.
0 Condition trace on address within range.
1 Condition trace on address outside of range.
3
DI1
Data access/instruction access trace 1.
0 Condition trace on data accesses.
1 Condition trace on instruction accesses.
2
DI2
Data access/instruction access trace 2.
0 Condition trace on data accesses.
1 Condition trace on instruction accesses.
Nexus Reg: 0xE Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Data Trace Start Address
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 36-22. Data Trace Start Address Register 1 (DTSA1)
Nexus Reg: 0xF Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Data Trace Start Address
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 36-23. Data Trace Start Address Register 2 (DTSA2)