NXP Semiconductors PXN2020, Reference Manual, Page: 146 / 1376

Clocks, Reset, and Power (CRP)
PXN20 Microcontroller Reference Manual, Rev. 1
6-14 Freescale Semiconductor
6.2.2.11 Power Status and Control Register (CRP_PSCR)
The power status and control register (CRP_PSCR) contains:
• Wakeup mode and source flags
• Sleep mode enable
• Sleep RAM retention select
Table 6-12. CRP_RECPTR Field Descriptions
Field Description
RECPTR Recovery Pointer. The RECPTR value is a generic 30-bit register available to the user application which retains
a value during all low-power modes. This register may be used by the user software to indicate where in RAM
a recovery routine exists.
FASTREC Fast Reset Recovery. Allows the reset sequence generated at the exit of a sleep mode to be shortened to 16
clocks. This bit may be used when the CRP_Z6VEC or CRP_Z0VEC register of the core(s) executing code
after a sleep mode points to a memory other than the flash. This allows code to be executed from those other
memories while the flash completes its internal initialization.
0 Reset occurs for 1000 clocks.
1 Reset occurs for 16 clocks.
Offset: CR 0x0060 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
SLEEP
F
0 0 0 0 0 0 0 0 0 0 0 0
RTC
OVR
WKF
RT
CWK
F
API
WKF
W w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
SLEEP
0 0 0 0
RAMSEL
0 0
0 0
WKC
LK
SEL
RTC
OVR
WK
EN
RTC
WK
EN
API
WK
EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 6-13. Power Status and Control Register (CRP_PSCR)
Table 6-13. CRP_PSCR Field Descriptions
Field Description
SLEEPF SLEEP Flag. The SLEEPF bit indicates whether recovery from the last low-power modes was sleep. While
SLEEPF is set, the pads remain in a safe state after Sleep mode recovery ad clearing SLEEPF will return the
pads to normal operation. A write of 1 clears this status flag and a write of 0 has no effect.
0 Low-power sleep mode was not entered.
1 Low-power sleep mode entered.
RTCOVRWKF RTC Counter Rollover Wakeup Flag. The RTCOVRWKF bit indicates that a RTC counter rollover was the
wakeup source. A write of 1 clears the interrupt flag and a write of 0 has no effect.
0 The RTC counter did not cause the last wakeup.
1 The RTC counter caused the last wakeup.