NXP Semiconductors PXN2020, Reference Manual, Page: 348 / 1376

Flash Memory Array and Control
PXN20 Microcontroller Reference Manual, Rev. 1
12-22 Freescale Semiconductor
Table 12-13. PFlash Supervisor Access Control Register (PFSACC) Field Descriptions
Field Description
SACC[30:0]
Supervisor Access Control. This bit field defines supervisor/user mode access control for each sector within
the main flash array.
0 Flash array sector n can be accessed in both user and supervisor mode.
1 Flash array sector n can be accessed only in supervisor mode. An attempted user mode access is
terminated with an AHB error response. If the requesting bus master is the processor core, the ERROR
response typically generates an instruction abort or data abort exception.
The mapping of this bit field to the main flash array is defined in Table 12-14
This field is initialized by hardware reset to the value contained in address 0x3E08 of the shadow block of the
flash array. An erased or unprogrammed flash sets this field to 0xFFFF_FFFF.
Table 12-14. {S,D}ACC Register to Flash Array Mapping
Register Bit
Starting Flash
Array Address
Sector Size
xACC[0] 0x00_0000 16 KB
xACC[1] 0x00_4000 16 KB
xACC[2] 0x00_8000 16 KB
xACC[3] 0x00_C000 16 KB
xACC[4] 0x01_0000 16 KB
xACC[5] 0x01_4000 16 KB
xACC[6] 0x01_8000 16 KB
xACC[7] 0x01_C000 16 KB
xACC[8] 0x02_0000 16 KB
xACC[9] 0x02_4000 16 KB
xACC[10] 0x02_8000 16 KB
xACC[11] 0x02_C000 16 KB
xACC[12] 0x03_0000 16 KB
xACC[13] 0x03_4000 16 KB
xACC[14] 0x03_8000 16 KB
xACC[15] 0x03_C000 16 KB
xACC[16] 0x04_0000 256 KB
xACC[17] 0x08_0000 256 KB
xACC[18] 0x0C_0000 256 KB
xACC[19] 0x10_0000 256 KB
xACC[20] 0x14_0000 256 KB
xACC[21] 0x18_0000 256 KB
xACC[22] 0x1C_0000 256 KB
xACC[23] 0x20_0000 256 KB
xACC[24] 0x24_0000 256 KB
xACC[25] 0x28_0000 256 KB
xACC[26] 0x2C_0000 256 KB
xACC[27] 0x30_0000 256 KB