NXP Semiconductors PXN2020, Reference Manual, Page: 533 / 1376

Enhanced Direct Memory Access Controller (eDMA)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 24-13
Both the eDMA request input signal and this enable request flag must be asserted before a channel’s
hardware service request is accepted. The state of the eDMA enable request flag does not effect a channel
service request made through software or a linked channel request.
As a given channel completes processing its major iteration count, there is a flag in the transfer control
descriptor that may affect the ending state of the EDMA_ERQR bit for that channel. If the TCD.D_REQ
bit is set, then the corresponding EDMA_ERQR bit is cleared after the major loop is complete, disabling
the eDMA hardware request. Otherwise if the D_REQ bit is cleared, the state of the EDMA_ERQR bit is
unaffected.
24.3.2.4 eDMA Enable Error Interrupt Register (EDMA_EEIRL)
The EDMA_EEIRL provides a bit map for the 32 channels to enable the error interrupt signal for each
channel. EDMA_EEIRL maps to channels 31–0.
The state of any given channel’s error interrupt enable is directly affected by writes to these registers; it is
also affected by writes to the EDMA_SEEIR and EDMA_CEEIR. The EDMA_SEEIR and
EDMA_CEEIR are provided so that the error interrupt enable for a single channel can be modified without
the performing a read-modify-write sequence to the EDMA_EEIRL.
Both the eDMA error indicator and this error interrupt enable flag must be asserted before an error
interrupt request for a given channel is asserted.
Offset: EDM 0x000C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R ERQ
31
ERQ
30
ERQ
29
ERQ
28
ERQ
27
ERQ
26
ERQ
25
ERQ
24
ERQ
23
ERQ
22
ERQ
21
ERQ
20
ERQ
19
ERQ
18
ERQ
17
ERQ
16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 19 19 20 21 22 23 24 25 26 27 28 29 30 31
R ERQ
15
ERQ
14
ERQ
13
ERQ
12
ERQ
11
ERQ
10
ERQ
09
ERQ
08
ERQ
07
ERQ
06
ERQ
05
ERQ
04
ERQ
03
ERQ
02
ERQ
01
ERQ
00
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 24-4. eDMA Enable Request Register (EDMA_ERQRL)
Table 24-5. EDMA_ERQRL Field Descriptions
Field Description
ERQn Enable eDMA Hardware Service Request n.
0 The eDMA request signal for channel n is disabled.
1 The eDMA request signal for channel n is enabled.