IEEE 1149.1 Test Access Port Controller (JTAGC)
PXN20 Microcontroller Reference Manual, Rev. 1
35-10
Freescale Semiconductor
35.4.4.1
BYPASS Instruction
BYPASS selects the bypass register, creating a single-bit shift register path between TDI and TDO.
BYPASS enhances test efficiency by reducing the overall shift path when no test operation of the MCU is
required. This allows more rapid movement of test data to and from other components on a board that are
required to perform test functions. While the BYPASS instruction is active, the system logic operates
normally.
35.4.4.2
ACCESS_AUX_TAP_x Instructions
The ACCESS_AUX_TAP_
x
instructions allow the Nexus modules on the MCU to take control of the TAP.
When this instruction is loaded, control of the TAP pins is transferred to the selected auxiliary TAP
controller. Any data input via TDI and TMS is passed to the selected TAP controller, and any TDO output
from the selected TAP controller is sent back to the JTAGC to be output on the pins. The JTAGC regains
control of the JTAG port during the UPDATE-DR state if the PAUSE-DR state was entered. Auxiliary TAP
controllers are held in RUN-TEST/IDLE while they are inactive.
Section 35.5, e200z0 and e200z6 OnCE Controllers,
for a block diagram and e200z0 OnCE controller
register descriptions.
35.4.4.3
CLAMP Instruction
CLAMP allows the state of signals driven from MCU pins to be determined from the boundary scan
register while the bypass register is selected as the serial path between TDI and TDO. CLAMP enhances
test efficiency by reducing the overall shift path to a single bit (the bypass register) while conducting an
EXTEST type of instruction through the boundary scan register. CLAMP also asserts the internal system
reset for the MCU to force a predictable internal state.
Factory Debug Reserved
1
00010
00011
00100
00101
00110
00111
01001
01010
01100
Intended for factory debug only
Reserved
2
All Other
Codes
Decoded to select bypass register
1
Intended for factory debug, and not customer use
2
Freescale reserves the right to change the decoding of reserved instruction codes in the future
Table 35-2. JTAG Instructions (continued)
Instruction
Code[4:0]
Instruction Summary
Summary of Contents for PXN2020
Page 1: ...PXN20 Microcontroller Reference Manual Devices Supported PXN2020 PXN2120 PXN20RM Rev 1 06 2011...
Page 42: ...PXN20 Microcontroller Reference Manual Rev 1 lxiv Freescale Semiconductor...
Page 64: ...Introduction PXN20 Microcontroller Reference Manual Rev 1 1 22 Freescale Semiconductor...
Page 112: ...Signal Description PXN20 Microcontroller Reference Manual Rev 1 3 44 Freescale Semiconductor...
Page 118: ...Resets PXN20 Microcontroller Reference Manual Rev 1 4 6 Freescale Semiconductor...
Page 372: ...e200z6 Core Z6 PXN20 Microcontroller Reference Manual Rev 1 13 8 Freescale Semiconductor...
Page 412: ...e200z0 Core Z0 PXN20 Microcontroller Reference Manual Rev 1 14 14 Freescale Semiconductor...
Page 821: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 Freescale Semiconductor 27 49...
Page 822: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 27 50 Freescale Semiconductor...
Page 1376: ...Memory Map PXN20 Microcontroller Reference Manual Rev 1 A 118 Freescale Semiconductor...