NXP Semiconductors PXN2020, Reference Manual, Page: 1146 / 1376

IEEE 1149.1 Test Access Port Controller (JTAGC)
PXN20 Microcontroller Reference Manual, Rev. 1
35-12 Freescale Semiconductor
35.4.5 Boundary Scan
The boundary scan technique allows signals at component boundaries to be controlled and observed
through the shift-register stage associated with each pad. Each stage is part of a larger boundary scan
register cell, and cells for each pad are interconnected serially to form a shift-register chain around the
border of the design. The boundary scan register consists of this shift-register chain, and is connected
between TDI and TDO when the EXTEST, SAMPLE, or SAMPLE/PRELOAD instructions are loaded.
The shift-register chain contains a serial input and serial output, as well as clock and control signals.
35.5 e200z0 and e200z6 OnCE Controllers
The e200z0 core OnCE controller supports a complete set of Nexus 1 debug features, as well as providing
access to the configuration registers. A complete discussion of the e200z0 OnCE debug features
is available in the
e200z0 Reference Manual .
The following sections describe functionality of the e200z0 OnCE controller; however, the e200z6 OnCE
controller operates in the same manner as the e200z0 OnCE controller, and is fully documented in the
e200z6 Reference Manual .
NOTE
The register select field in the e200z6 OnCE command register
(OCMD[RS]) does not implement the shared nexus control register (SNC).
35.5.1 e200z0 OnCE Controller Block Diagram
Figure 35-7 is a block diagram of the e200z0 OnCE block.