NXP Semiconductors PXN2020, Reference Manual, Page: 46 / 1376

Introduction
PXN20 Microcontroller Reference Manual, Rev. 1
1-4 Freescale Semiconductor
1.4 PXN21 Block Diagram
Figure 1-2 shows a top-level block diagram for the PXN21.
Figure 1-2. PXN21 Block Diagram
Crossbar Switch (XBAR)
Memory Protection Unit (MPU)
PXN21 Block Diagram
VLE
MMU (32 TLB)
32 KB Cache
e200z650 Core
FPU/SPE
JTAG
Nexus3 (Z6)
(Z0)
4/8 Way
4–40 MHz
XTAL
Masters
32 kHz
XTAL
16 MHz
IRC
VREG
Controller
e200z0 Core
VLE
Semaphores
32-ch DMA
Mux
128 kHz
IRC
FMPLL
SWT
STM
RTC/API
INTC
PIT
BAM
SIU
2 MB
ECSM
128 KB
Standby RAM
ECSM
PBRIDGE B
2 x I
2
C
2 x SPI
5 x CAN
PBRIDGE A
4 x UART/LIN
2 x SPI
2 x I
2
C
SRAM
(ECC)
Flash
(ECC)
CTU
Debug
MPU – Memory protection unit
NDI – Nexus debug interface
PBRIDGE – Peripheral I/O bridge
PIT
– Periodic interrupt timer
RTC – Real time clock
SIU – System integration unit
SPI – Serial peripheral interface controller
STM – System timer module
SWT – Software watchdog timer
UART/LIN – Universal asynchronous receiver/transmitter/
local interconnect network
VREG – Voltage regulator
ADC – Analog-to-digital converter
BAM – Boot assist module
CAN – Controller area network controller
CTU – Cross triggering unit
ECC – Error correction code
ECSM – Error correction status module
eDMA – Enhanced direct memory access controller
eMIOS – Timed input/output
FMPLL – Frequency-modulated phase-locked loop
I
2
C – Inter-integrated circuit controller
INTC – Interrupt controller
JTAG – Joint Test Action Group interface
8 x UART/LIN
32 x eMIOS
64 x ADC