FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
26-42
Freescale Semiconductor
26.5.2.31 Sync Frame Counter Register (SFCNTR)
This register provides the number of synchronization frames that are used for clock synchronization in the
last even and in the last odd numbered communication cycle. This register is updated after the start of the
NIT and before 10 MT after offset correction start.
NOTE
If the application has locked the even synchronization table at the end of the
static segment of an even communication cycle, the controller will not
update the fields SFEVB and SFEVA.
If the application has locked the odd synchronization table at the end of the
static segment of an odd communication cycle, the controller will not update
the values SFODB and SFODA.
26.5.2.32 Sync Frame Table Offset Register (SFTOR)
This register defines the FlexRay Memory related offset for sync frame tables. For more details, see
Section 26.6.12, Sync Frame ID and Sync Frame Deviation Tables.
Base + 0x0040
Additional Reset: RUN Command
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
SFEVB
SFEVA
SFODB
SFODA
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-31. Sync Frame Counter Register (SFCNTR)
Table 26-37. SFCNTR Field Descriptions
Field
Description
SFEVB
Sync Frames Channel B, even cycle — protocol related variable: size of (
vsSyncIdListB
for even cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for clock
synchronization.
SFEVB
Sync Frames Channel A, even cycle — protocol related variable: size of (
vsSyncIdListA
for even cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for clock
synchronization.
SFODB
Sync Frames Channel B, odd cycle — protocol related variable: size of (
vsSyncIdListB
for odd cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for clock
synchronization.
SFODA
Sync Frames Channel A, odd cycle — protocol related variable: size of (
vsSyncIdListA
for odd cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for clock
synchronization.
Base + 0x0042
Write:
POC:config
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
SFT_OFFSET[15:1]
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-32. Sync Frame Table Offset Register (SFTOR)
Summary of Contents for PXN2020
Page 1: ...PXN20 Microcontroller Reference Manual Devices Supported PXN2020 PXN2120 PXN20RM Rev 1 06 2011...
Page 42: ...PXN20 Microcontroller Reference Manual Rev 1 lxiv Freescale Semiconductor...
Page 64: ...Introduction PXN20 Microcontroller Reference Manual Rev 1 1 22 Freescale Semiconductor...
Page 112: ...Signal Description PXN20 Microcontroller Reference Manual Rev 1 3 44 Freescale Semiconductor...
Page 118: ...Resets PXN20 Microcontroller Reference Manual Rev 1 4 6 Freescale Semiconductor...
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Page 1376: ...Memory Map PXN20 Microcontroller Reference Manual Rev 1 A 118 Freescale Semiconductor...