NXP Semiconductors PXN2020, Reference Manual, Page: 481 / 1376

Software Watchdog Timer (SWT)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 20-3
Offset: SW 0x0000 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R MAP
0
MAP
1
MAP
2
MAP
3
MAP
4
MAP
5
MAP
6
MAP
7
0 0 0 0 0 0 0 0
W
Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0
KEY RIA WND ITR HLK SLK
0 0
FRZ WEN
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1
Figure 20-1. SWT Control Register (SWT_CR)
Table 20-2. SWT_CR Field Descriptions
Field Description
MAPn Master Access Protection for Master n. The PXN20 bus master assignments are shown in the following table.
0 Access for the master is not enabled
1 Access for the master is enabled.
KEY Keyed Service Mode.
0 Fixed Service Sequence, the fixed sequence 0xA602, 0xB480 is used to service the watchdog.
1 Keyed Service Mode, two pseudorandom key values are used to service the watchdog.
RIA Reset on Invalid Access.
0 Invalid access to the SWT generates a bus error.
1 Invalid access to the SWT causes a system reset if WEN = 1.
WND Window Mode.
0 Regular mode, service sequence can be done at any time.
1 Windowed mode, the service sequence is only valid when the down counter is less than the value in the
SWT_WN register.
ITR Interrupt Then Reset.
0 Generate a reset on a time-out.
1 Generate an interrupt on an initial time-out, reset on a second consecutive time-out.
HLK Hard Lock. This bit is only cleared at reset.
0 SWT_CR, SWT_TO, SWT_WN and SWT_SK are read/write registers if SLK = 0.
1 SWT_CR, SWT_TO, SWT_WN and SWT_SK are read-only registers.
Bit
Bus Master
Bit
Bus Master
MAP0 0 — Z6 Core MAP4 4 — FEC
MAP1 1 — Z0 Core MAP5 5 — MLB
MAP2 2 — eDMA MAP6 6 — FlexRay
MAP3 3 — not used MAP7 7 — not used