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Controller Area Network (FlexCAN)
PXN20 Microcontroller Reference Manual, Rev. 1
29-6
Freescale Semiconductor
The FlexCAN module stores CAN messages for transmission and reception using a message buffer
structure. Each MB is formed by 16 bytes mapped in memory as described in
. The FlexCAN
module can manage as many as 64 message buffers.
shows a standard/extended message buffer
(MB0) memory map, using 16 bytes (0x80–0x8F) total space.
NOTE
Reading the C/S word of a message buffer (the first word of each MB) locks
it, preventing it from receiving further messages until it is unlocked either
by reading another MB or by reading the timer.
NOTE
During CAN messages reception by FlexCAN, the RXGMASK (Rx Global
Mask) is used as acceptance mask for most of the Rx Message Buffers
(MB). When the FIFO Enable bit in the FlexCAN Module Configuration
Register (CANx_MCR[FEN], bit 2) is set, the RXGMASK also applies to
most of the elements of the ID filter table. However there is a misalignment
between the position of the ID field in the Rx MB and in RXIDA, RXIDB,
and RXIDC fields of the ID Tables. In fact RXIDA filter in the ID Tables is
shifted one bit to the left from Rx MBs ID position as shown below:
•
Rx MB ID = bits 3-31 of ID word corresponding to message ID bits 0-28
•
RXIDA = bits 2-30 of ID Table corresponding to message ID bits 0-28
Note that the mask bits one-to-one correspondence occurs with the filters
bits, not with the incoming message ID bits. This leads the RXGMASK to
affect Rx MB and Rx FIFO filtering in different ways. For example, if the
user intends to mask out the bit 24 of the ID filter of Message Buffers then
the RXGMASK will be configured as 0xffff_ffef. As result, bit 24 of the ID
field of the incoming message will be ignored during filtering process for
Message Buffers. This very same configuration of RXGMASK would lead
bit 24 of RXIDA to be "don't care" and thus bit 25 of the ID field of the
incoming message would be ignored during filtering process for Rx FIFO.
Similarly, both RXIDB and RXIDC filters have multiple misalignments
with regards to position of ID field in Rx MBs, which can lead to erroneous
masking during filtering process for either Rx FIFO or MBs. RX14MASK
(Rx 14 Mask) and RX15MASK (Rx 15 Mask) have the same structure as
the RXGMASK. This includes the misalignment problem between the
position of the ID field in the Rx MBs and in RXIDA, RXIDB, and RXIDC
fields of the ID Tables.
Table 29-2. Message Buffer MB0 Memory Mapping
Address
Offset
MB Field
0x80
Control and status (C/S)
0x84
Identifier field
0x88–0x8F
Data fields 0–7 (1 byte each)
Summary of Contents for PXN2020
Page 1: ...PXN20 Microcontroller Reference Manual Devices Supported PXN2020 PXN2120 PXN20RM Rev 1 06 2011...
Page 42: ...PXN20 Microcontroller Reference Manual Rev 1 lxiv Freescale Semiconductor...
Page 64: ...Introduction PXN20 Microcontroller Reference Manual Rev 1 1 22 Freescale Semiconductor...
Page 112: ...Signal Description PXN20 Microcontroller Reference Manual Rev 1 3 44 Freescale Semiconductor...
Page 118: ...Resets PXN20 Microcontroller Reference Manual Rev 1 4 6 Freescale Semiconductor...
Page 372: ...e200z6 Core Z6 PXN20 Microcontroller Reference Manual Rev 1 13 8 Freescale Semiconductor...
Page 412: ...e200z0 Core Z0 PXN20 Microcontroller Reference Manual Rev 1 14 14 Freescale Semiconductor...
Page 821: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 Freescale Semiconductor 27 49...
Page 822: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 27 50 Freescale Semiconductor...
Page 1376: ...Memory Map PXN20 Microcontroller Reference Manual Rev 1 A 118 Freescale Semiconductor...