NXP Semiconductors PXN2020, Reference Manual, Page: 972 / 1376

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
30-46 Freescale Semiconductor
Figure 30-29. DSPI Transfer Timing Diagram (MTFE = 0, CPHA = 0, FMSZ = 8)
The master initiates the transfer by placing its first data bit on the SOUT x pin and asserting the appropriate
peripheral chip select signals to the slave device. The slave responds by placing its first data bit on its
SOUT pin. After the
t
CSC
delay has elapsed, the master outputs the first edge of SCK. This is the edge used
by the master and slave devices to sample the first input data bit on their serial data input signals. At the
second edge of the SCK, the master and slave devices place their second data bit on their serial data output
signals. For the rest of the frame the master and the slave sample their SIN pins on the odd-numbered clock
edges and changes the data on their SOUT pins on the even-numbered clock edges. After the last clock
edge occurs a delay of t
ASC
is inserted before the master negates the PCS signals. A delay of t
DT
is inserted
before a new frame transfer can be initiated by the master.
For the CPHA = 0 condition of the master, TCF and EOQF are set and the RXCTR counter is updated at
the next to last serial clock edge of the frame (edge 15) of
Figure 30-29 .
For the CPHA = 0 condition of the slave, TCF is set and the RXCTR counter is updated at the last serial
clock edge of the frame (edge 16) of
Figure 30-29 .
30.4.8.2 Classic SPI Transfer Format (CPHA = 1)
This transfer format shown in Figure 30-30 is used to communicate with peripheral SPI slave devices that
require the first SCK edge before the first data bit becomes available on the slave SOUT pin. In this format
the master and slave devices change the data on their SOUT pins on the odd-numbered SCK edges and
sample the data on their SIN pins on the even-numbered SCK edges
SCK
(CPOL = 0)
PCSx/SS
t
ASC
SCK
(CPOL = 1)
Master & Slave
Sample
Master SOUT/
Slave SIN
Master SIN/
Slave SOUT
Bit 6
Bit 1 Bit 5
Bit 2 Bit 4
Bit 3 Bit 3
Bit 4 Bit 2
Bit 5 Bit 1
Bit 6 LSB
MSB
MSB
LSB
t
DT
t
CSC
t
CSC
MSB First (LSBFE = 0):
LSB First (LSBFE = 1):
t
CSC
= PCS to SCK delay.
t
ASC
= After SCK delay.
t
DT
= Delay after transfer (minimum CS idle time).
Master (CPHA = 0): TCF and EOQF are set and RXCTR counter
is updated at next to last SCK edge of frame (edge 15)
Slave (CPHA = 0): TCF is set and RXCTR counter is updated at
last SCK edge of frame (edge 16)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15