NXP Semiconductors PXN2020, Reference Manual, Page: 973 / 1376

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 30-47
Figure 30-30. DSPI Transfer Timing Diagram (MTFE = 0, CPHA = 1, FMSZ = 8)
The master initiates the transfer by asserting the PCS signal to the slave. After the
t
CSC
delay has elapsed,
the master generates the first SCK edge and at the same time places valid data on the master SOUT pin.
The slave responds to the first SCK edge by placing its first data bit on its slave SOUT pin.
At the second edge of the SCK the master and slave sample their SIN pins. For the rest of the frame the
master and the slave change the data on their SOUT pins on the odd-numbered clock edges and sample
their SIN pins on the even-numbered clock edges. After the last clock edge occurs a delay of
t
ASC
is inserted
before the master negates the PCS signal. A delay of t
DT
is inserted before a new frame transfer can be
initiated by the master.
For CPHA = 1 the master EOQF and TCF and slave TCF are set at the last serial clock edge (edge 16) of
Figure 30-30 . For CPHA = 1 the master and slave RXCTR counters are updated on the same clock edge.
30.4.8.3 Modified SPI/DSI Transfer Format (MTFE = 1, CPHA = 0)
In this modified transfer format, both the master and the slave sample later in the SCK period than in
classic SPI mode to allow for delays in device pads and board traces. These delays become a more
significant fraction of the SCK period as the SCK period decreases with increasing baud rates.
NOTE
For correct operation of the modified transfer format, the user must
thoroughly analyze the SPI link timing budget.
The master and the slave place data on the SOUT pins at the assertion of the PCS signal. After the PCS to
SCK delay has elapsed, the first SCK edge is generated. The slave samples the master SOUT signal on
Slave (CPHA = 1): TCF is set and RXCTR counter is updated at
last SCK edge of frame (edge 16)
SCK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
(CPOL = 0)
PCSx/SS
t
ASC
SCK
(CPOL = 1)
Master & Slave
Sample
Master SOUT/
Slave SIN
Master SIN/
Slave SOUT
Bit 6
Bit 1 Bit 5
Bit 2 Bit 4
Bit 3 Bit 3
Bit 4 Bit 2
Bit 5 Bit 1
Bit 6 LSB
MSB
MSB
LSB
t
DT
t
CSC
MSB First (LSBFE = 0):
LSB First (LSBFE = 1):
t
CSC
= PCS to SCK delay.
t
ASC
= After SCK delay.
t
DT
= Delay after transfer (minimum CS negation time).
Master (CPHA = 1): TCF and EOQF are set and RXCTR counter
is updated at last SCK edge of frame (edge 16)
16