NXP Semiconductors PXN2020, Reference Manual, Page: 995 / 1376

Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 31-5
NOTE
eSCI_G, eSCI_H, eSCI_J, eSCI_K, eSCI_L, and eSCI_M are not
implemented on the PXN20.
31.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Writes to a reserved register location do not have any effect and
reads of these locations return a 0. Details of register bit and field function follow the register diagrams,
in bit order.
Table 31-1. eSCI Memory Map
Offset from
ESCI_BASE
eSCI_A = 0xFFFA_0000
eSCI_B = 0xFFFA_4000
eSCI_C = 0xFFFA_8000
eSCI_D = 0xFFFA_C000
eSCI_E = 0xFFFB_0000
eSCI_F = 0xFFFB_4000
eSCI_G = 0xFFFB_8000
eSCI_H = 0xFFFB_C000
eSCI_J = 0xC3FA_0000
eSCI_K = 0xC3FA_4000
eSCI_L = 0xC3FA_8000
eSCI_M = 0xC3FA_C000
Register Access
Reset
Value
Section/Page
0x0000 eSCI_BRR—eSCI baud rate register R/W 0x0004 31.3.2.1/31-6
0x0002 eSCI_CR1—eSCI control register 1 R/W 0x0000 31.3.2.2/31-6
0x0004 eSCI_CR2—eSCI control register 2 R/W 0xA000 31.3.2.3/31-8
0x0006 eSCI_SDR—eSCI data register R/W 0x0000 31.3.2.4/31-10
0x0008 eSCI_IFSR1—eSCI interrupt flag and status register 1 R/W 0x8000 31.3.2.5/31-11
0x000A eSCI_IFSR2—eSCI interrupt flag and status register 2 R/W 0x4000 31.3.2.6/31-12
0x000C eSCI_LCR1—eSCI LIN control register 1 R/W 0x0000 31.3.2.7/31-13
0x000E eSCI_LCR2—eSCI LIN control register 2 R/W 0x0000 31.3.2.8/31-15
0x00010 eSCI_LTR— eSCI LIN transmit register R/W 0x0000 31.3.2.9/31-15
0x0012 Reserved
0x0014 eSCI_LRR—eSCI LIN receive register R/W 0x0000 31.3.2.10/31-17
0x0016 Reserved
0x0018 eSCI_LPR—eSCI LIN CRC polynomial register R/W 0xC599 31.3.2.11/31-18
0x001A eSCI_CR3—eSCI control register 3 R/W 0x0000 31.3.2.12/31-18
0x001C–0x3FFF Reserved