NXP Semiconductors PXN2020, Reference Manual, Page: 129 / 1376

System Clock Description
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 5-11
5.4.2 Halt Clock Gating
System clock gating is forced via the centralized halt mechanism. The SIU_HLT0 and SIU_HLT1 bits
corresponding to individual modules are configured to determine which modules are clock gated.
The SIU_HLT0 and SIU_HLT1 bits are used to drive the stop inputs to the modules. After the module
completes a clean shutdown, the module asserts the stop acknowledge handshake. The stop acknowledge
is visible in the SIU_HLTACK0 and SIU_HLTACK1 read-only register bits. The modules are individually
controlled and halted.
The halted module recovers when the HLT bit is cleared by software. After HLT is cleared, the device’s
logic re-enables the clocks to the modules and negates the stop signal after the required timing has been
met.
There is no hardware disable for the eDMA and FlexRay modules. Thus before setting the HLT bits for
these masters, software should take actions to prepare for the eDMA and FlexRay clocks to be stopped.
Then software sets the HLT bits for the eDMA and FlexRay to indicate to the clock logic that the clocks
to these modules can now be stopped.
When the Z0 and Z6 have executed WAIT instructions, then the clocks to the platform are also gated. The
platform logic includes the MPU, AXBS, AIPS, and ECSM. The INTC and SIU are not clock gated to
allow for an interrupt to be used to exit WAIT.
5.4.3 Core WAIT Clock Gating
Core clock gating is enabled via the CPU WAIT instruction.
Table 5-2. Software-Controlled Clock Gating Support
Block Name Register Name Bit Name
DSPI DSPI_MCR
Offset: Base + 0x0000
MDIS
ESCI ESCIx_CR2
Offset: Base + 0x0004
MDIS
FlexCAN CANx_MCR
Offset: Base + 0x0000
MDIS
EMIOS EMIOS_MCR
Offset: Base + 0x0000
MDIS
CTU CTUPCR
Offset: Base + 0x00CC
MDIS
PIT PITCTRL
Offset: Base + 0x0110
MDIS
I
2
C IBCR
Offset: Base + 0x0002
MDIS
NPC Nexus PCR[30]= MCKO_GT
Nexus PCR[29]= MCKO_EN==MDIS
Reg Index: 127
MCKO_EN,
MCKO_GT