NXP Semiconductors PXN2020, Reference Manual, Page: 221 / 1376

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 8-39
8.3.2.23 Halt Register (SIU_HLTn)
The SIU_HLT n register is used to halt the various peripherals by disabling the clocks to the module.
Writing a 1 to a HLT n bit drives a separate halt request to the associated peripheral. After completing any
task in progress, the peripheral shuts down its clock input and signals to the SIU_HLTACK n register that
it has halted. Writing a 0 to a HLT n bit drives a separate request to the associated peripheral causes the
peripheral to restart its clock input and signals to the SIU_HLTACK n register that it has restarted.
Writes to bits in SIU_HLT n that are not associated with a peripheral are reflected in the SIU_HLT n register
and in the SIU_HLTACK n register, but have no other effect.
Table 8-26. SIU_SYSCLK Field Descriptions
Field Description
SYSCLKSEL System Clock Select. The SYSCLKSEL bit selects the source for the system clock.
00 System clock supplied by 16 MHz IRC.
01 System clock supplied by 4 – 40 MHz_XTAL.
10 System clock supplied by FMPLL.
11 Reserved (defaults to 16 MHz IRC).
Note: The default SYSCLKSEL value may be modified by the BAM code execution to 0b01 to select the
4–40 MHz XTAL as the system clock source to support the serial download operation. Please see
Chapter 9, Boot Assist Module (BAM), for more details.
SYSCLKDIV System Clock Divide. The SYSCLKDIV bits select the divider value for the system clock. The SYSCLKDIV
divider is required in addition to the RFD to allow the other sources for the system clock (16 MHz IRC and
4 – 40 MHz XTAL) to be divided to slowest frequencies to improve power consumption.
000 Divide by 1.
001 Divide by 2.
010 Divide by 4.
011 Divide by 8.
100 Divide by 16.
101 – 111 Reserved (defaults to divide by 1).
LPCLKDIVn Low-Power Peripheral Clock Divides. The LPCLKDIV bits select the divider values for each peripheral group.
00 Divide by 1.
01 Divide by 2.
10 Divide by 4.
11 Divide by 8.
LPCLKDIVn
Peripheral Set Number Peripheral Groups
LPCLKDIV0 Peripheral Set 1 eSCI, I
2
C
LPCLKDIV1 Peripheral Set 2 FlexCAN, SPI
LPCLKDIV2 Peripheral Set 3 ADC, CTU
LPCLKDIV3 Peripheral Set 4 eMIOS