NXP Semiconductors PXN2020, Reference Manual, Page: 1368 / 1376

Memory Map
PXN20 Microcontroller Reference Manual, Rev. 1
A-110 Freescale Semiconductor
0x09B8 SIU_EMIOS_SEL1—eMIOS select register 1 R/W 0x0000_0000 8.3.2.25/8-44
0x09BC SIU_EMIOS_SEL2—eMIOS select register 2 R/W 0x0000_0000 8.3.2.25/8-44
0x09C0 SIU_EMIOS_SEL3—eMIOS select register 3 R/W 0x0000_0000 8.3.2.25/8-44
0x09C4 SIU_ISEL2A—External interrupt select register 2A R/W 0x0000_0000 8.3.2.26/8-45
0x09C8–0x0BFF Reserved
0x0C00 SIU_PGPDO0—Parallel GPIO pin data output register 0 R/W 0x0000_0000 8.3.2.27/8-48
0x0C04 SIU_PGPDO1—Parallel GPIO pin data output register 1 R/W 0x0000_0000 8.3.2.28/8-48
0x0C08 SIU_PGPDO2—Parallel GPIO pin data output register 2 R/W 0x0000_0000 8.3.2.29/8-49
0x0C0C SIU_PGPDO3—Parallel GPIO pin data output register 3 R/W 0x0000_0000 8.3.2.30/8-49
0x0C10 SIU_PGPDO4—Parallel GPIO pin data output register 4 R/W 0x0000_0000 8.3.2.31/8-49
0x0C14–0x0C3F Reserved
0x0C40 SIU_PGPDI0—Parallel GPIO pin data input register 0 R/W —
3
8.3.2.32/8-50
0x0C44 SIU_PGPDI1—Parallel GPIO pin data input register 1 R/W —
3
8.3.2.33/8-50
0x0C48 SIU_PGPDI2—Parallel GPIO pin data input register 2 R/W —
3
8.3.2.34/8-51
0x0C4C SIU_PGPDI3—Parallel GPIO pin data input register 3 R/W —
3
8.3.2.35/8-51
0x0C50 SIU_PGPDI4—Parallel GPIO pin data input register 4 R/W —
3
8.3.2.36/8-52
0x0C54–0x0C83 Reserved
0x0C84 SIU_MPGPDO1—Masked parallel GPIO data output register 1 R 0x0000_0000 8.3.2.37/8-52
0x0C88 SIU_MPGPDO2—Masked parallel GPIO data output register 2 R 0x0000_0000 8.3.2.38/8-53
0x0C8C SIU_MPGPDO3—Masked parallel GPIO data output register 3 R 0x0000_0000 8.3.2.39/8-53
0x0C90 SIU_MPGPDO4—Masked parallel GPIO data output register 4 R 0x0000_0000 8.3.2.40/8-54
0x0C94 SIU_MPGPDO5—Masked parallel GPIO data output register 5 R 0x0000_0000 8.3.2.41/8-54
0x0C98 SIU_MPGPDO6—Masked parallel GPIO data output register 6 R 0x0000_0000 8.3.2.42/8-55
0x0C9C SIU_MPGPDO7—Masked parallel GPIO data output register 7 R 0x0000_0000 8.3.2.43/8-55
0x0CA0 SIU_MPGPDO8—Masked parallel GPIO data output register 8 R 0x0000_0000 8.3.2.44/8-56
0x0CA4 SIU_MPGPDO9—Masked parallel GPIO data output register 9 R 0x0000_0000 8.3.2.45/8-56
0x0CA8–0x0CFF Reserved
0x0D00 SIU_DSPIAH—Masked serial GPO register for DSPI_A High R/W 0x0000_0000 8.3.2.46/8-57
0x0D04 SIU_DSPIAL—Masked serial GPO register for DSPI_A Low R/W 0x0000_0000 8.3.2.47/8-58
0x0D08 SIU_DSPIBH—Masked serial GPO register for DSPI_B High R/W 0x0000_0000 8.3.2.48/8-58
0x0D0C SIU_DSPIBL—Masked serial GPO register for DSPI_B Low R/W 0x0000_0000 8.3.2.49/8-59
0x0D10 SIU_DSPICH—Masked serial GPO register for DSPI_C High R/W 0x0000_0000 8.3.2.50/8-60
Table A-4. PXN20 Detailed Register Map (continued)
Address Offset
from Module Base
Register Access
1
Reset Value
2
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