NXP Semiconductors PXN2020, Reference Manual, Page: 853 / 1376

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 28-31
28.4.1.1.7 Pulse/Edge Accumulation (PEA) Mode
The PEA mode returns the time taken to detect a desired number of input events. MODE[6] bit selects
between continuous or single shot operation.
After writing to register A1, the internal counter is cleared on the first input event, ready to start counting
input events and the selected timebase is latched into register B2. On the match between the internal
counter and register A1, a counter bus capture is triggered to register A2 and B2. The data previously held
in register B2 is transferred to register B1 and the FLAG bit is set to indicate that an event has occurred.
The desired time interval can be determined by subtracting register B1 from A2. Registers
EMIOS_CADR[
n ] and EMIOS_CBDR[ n ] return the values in register A2 and B1, respectively.
As part of the coherency mechanism, reading EMIOS_CADR[ n ] disables transfers from B2 to B1. These
transfers are disabled until the next read of the EMIOS_CBDR[ n ] register. Reading the EMIOS_CBDR[ n ]
register re-enables transfers from B2 to B1, to take effect at the next transfer event, as previously
described.
1
In order to have coherent data in continuous mode of operation the following steps should be performed,
assuming FLAG is initially cleared:
1. Wait for FLAG assertion.
2. Read EMIOS_CADR[ n ] register.
3. Read EMIOS_CBDR[ n ] register.
4. Clear FLAG bit.
5. Return to step #1.
Accumulation cycles may be lost if the read is not performed in a timely manner. Whenever the Overrun
bit is asserted it means that one or more cycles have been lost.
Triggering of the counter clock (input event) is done by a rising or falling edge or both edges on the input
pin. The polarity of the triggering edge is selected by the EDSEL and EDPOL bits in EMIOS_CCR[
n ]
register.
For continuous operation mode (MODE[0] cleared, MODE[0:6] = 000_1000), the counter is cleared on
the next input event after a FLAG generation and continues to operate as previously described.
For single shot operation (MODE[0] set, MODE[0:6] = 000_1001), the counter is not cleared or
incremented after a FLAG generation until a new writing operation to register A is performed.
Figure 28-27 and Figure 28-28 show how the Unified Channel can be used for continuous and single shot
pulse/edge accumulation mode.
1. If B1 was not updated due to B2 to B1 transfer being disabled after reading register EMIOS_CADR[n], further
EMIOS_CADR[n] and EMIOS_CBDR[n] reads will not return coherent data until a new bus capture is triggered to registers A2
and B2. This capture event is indicated by the channel FLAG being asserted. If enabled, the FLAG also generates an interrupt.