NXP Semiconductors PXN2020, Reference Manual, Page: 627 / 1376

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-13
26.5.2.2.2 Register Write Access Requirements
All registers can be accessed with 8-bit, 16-bit and 32-bit wide operations. For some of the registers, at
least a 16-bit wide write access is required to ensure correct operation. This write access requirement is
stated in the detailed register description for each register affected
26.5.2.2.3 Internal Register Access
The following memory mapped registers are used to access multiple internal registers.
• Strobe Signal Control Register (STBSCR)
• Slot Status Selection Register (SSSR)
• Slot Status Counter Condition Register (SSCCR)
• Receive Shadow Buffer Index Register (RSBIR)
Each of these memory mapped registers provides a SEL field and a WMD bit. The SEL field is used to
select the internal register. The WMD bit controls the write mode. If the WMD bit is set to 0 during the
write access, all fields of the internal register are updated. If the WMD bit set to 1, only the SEL field is
changed. All other fields of the internal register remain unchanged. This allows for reading back the values
of the selected internal register in a subsequent read access.
26.5.2.3 Module Version Register (MVR)
This register provides the controller version number. The module version number is derived from the CHI
version number and the PE version number.
Table 26-6. Register Write Access Restrictions
Condition Indication Description
Any Time — No write access restriction.
Disabled Mode MCR[MEN] = 0 Write access only when the controller is in Disabled Mode.
Normal Mode MCR[MEN] = 1 Write access only when the controller is in Normal Mode.
POC:config PSR0[PROTSTATE] = POC:config Write access only when the Protocol is in the POC:config state.
MB_DIS MBCCSRn[EDS] = 0 Write access only when the related Message Buffer is disabled.
MB_LCK MBCCSRn[LCKS] = 1 Write access only when the related Message Buffer is locked.
Base + 0x0000
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R CHIVER PEVER
W
Reset 1 0 0 1 1 1 0 1 0 1 1 0 0 1 1 0
Figure 26-2. Module Version Register (MVR)
Table 26-7. MVR Field Descriptions
Field Description
CHIVER CHI Version Number—This field provides the version number of the controller host interface.
PEVER PE Version Number—This field provides the version number of the protocol engine.