NXP Semiconductors PXN2020, Reference Manual, Page: 981 / 1376

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 30-55
unchanged in this mode with respect to the other modes and remain controlled by the CSC and ASC delay
fields respectively when not in continuous SCK mode.
30.4.10.2 TSB Command Frame Format
In the TSB configuration a command frame is shown in Figure 30-40 .
Figure 30-40. Command Frame Format
In the active phase of the command frame, the chip select becomes active validating the SOUT and SCK
output signals. Outside the active phase, chip select is at passive level and invalid data may occur at SOUT.
For TSB configuration, assuming CPOL = 0, the SOUT output and the chip select changes its state always
with the SCK rising edge. The SOUT signal must be sampled in the slave device with the falling edge of
SCK. The clock period of SCK is defined as T
SCK
. The length of the command frame passive phase T
DT
should always be fixed to a minimum of 1x T
SCK
.
30.4.10.3 TSB Data Frame Format
A data frame is transmitted from the TSB controller to the receiving devices. Figure 30-41 details the
frame active and passive phase,
For TSB configuration assuming CPOL = 0, the SOUT output and the chip select change their states
always with the SCK rising edge. The SOUT signal must be sampled in the receiving device with the
falling edge of SCK. The length of the data frame passive phase T
DT
can be a minimum of 1 × T
SCK
.
A data frame can be composed by data bits only or by data bits preceded by a selection bit, see
Figure 30-41 . A data frame with a selection bit always starts with a low level bit at SOUT.
The number of data bits in the active phase is from 4 to 32 bits, and the least significant bit of a data portion
is transmitted first (LSBFE = 1).
SCK
PCS
Master SOUT
Invalid
Command Frame
t
DT
Command Frame = 0 to 32 bits
LSB
1
Command Selection Bit
(CPOL = 0)
Active Phase
t
DT
= from 1 to (PDT * DT / Fsys)T
SCK