NXP Semiconductors PXN2020, Reference Manual, Page: 551 / 1376

Enhanced Direct Memory Access Controller (eDMA)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 24-31
Minor loop TCD variables are SOFF, SMOD, DOFF, DMOD, NBYTES, SADDR, DADDR,
BWC, ACTIVE, AND START. Major loop TCD variables are DLAST, SLAST, CITER,
BITER, DONE, D_REQ, INT_MAJ, MAJOR_LNKCH, and INT_HALF.
For descriptors where the sizes are not equal, multiple access of the smaller size data are
required for each reference of the larger size. For example, if the source size references 16-bit
data and the destination is 32-bit data, two reads are performed, then one 32-bit write.
• TCD local memory
— Memory controller: This logic implements the required dual-ported controller, handling
accesses from both the DMA engine as well as references from the slave bus. As noted earlier,
in the event of simultaneous accesses, the DMA engine is given priority and the slave
transaction is stalled.
— Memory array: The TCD is implemented using a single-ported, synchronous compiled RAM
memory array.
24.4.1 eDMA Basic Data Flow
The eDMA transfers data based on a two-deep, nested flow. The basic flow of a data transfer can be
partitioned into three segments. As shown in
Figure 24-19 , the first segment involves the channel service
request. In the diagram, this example uses the assertion of the eDMA peripheral request signal to request
service for channel
n . Channel service request via software and the TCDn.START bit follows the same
basic flow as an eDMA peripheral request. The eDMA peripheral request input signal is registered
internally and then routed to through the DMA engine, first through the control module, then into the
program model/channel arbitration module. In the next cycle, the channel arbitration is performed using
the fixed-priority or round-robin algorithm. After the arbitration is complete, the activated channel number
is sent through the address path and converted into the required address to access the TCD local memory.
Next, the TCD memory is accessed and the required descriptor read from the local memory and loaded
into the DMA engine address path channel{x,y} registers. The TCD memory is organized 64-bits in width
to minimize the time needed to fetch the activated channel’s descriptor and load it into the eDMA engine
address path channel{x,y} registers.