NXP Semiconductors PXN2020, Reference Manual, Page: 1131 / 1376

Analog-to-Digital Converter (ADC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 34-51
NOTE
If the higher threshold for the analog watchdog is programmed lower than
the lower threshold and the converted value is lesser than the lower
threshold then the WDG
n L interrupt for the low threshold violation is set,
else if the converted value is greater than the lower threshold (consequently
also greater than the higher threshold) then the interrupt WDG
n H for high
threshold violation is set. Thus the user should take care of avoiding that
situation as it could lead to misinterpretation of the watchdog interrupts.
34.4.5.1 Analog Watchdog Pulse Width Modulation Bus
For each input channel, an output bus is used to signal outside the result of the comparison generating
modulated pulse waveforms based on the converted analog values received by the analog watchdogs:
• If the converted data value is lower than the lower threshold, then the output pin (and THROP bit
in TRC
n register) is forced high.
• If the converted voltage is higher than the higher threshold, then the output pin (and THROP bit in
TRC
n register) is forced low.
• If the converted voltage lies between the upper and the lower threshold guard window, then the
output pin (and THROP bit in TRC
n register) keeps its logic value.
The logic level of the output pin can be programmed by software. In fact, the user can decide to keep the
behavior described or to invert the output logic level by setting the THRINV bit in the TRC
n register.
The values set on the ad_awpwm bus remain same in case the alternate watchdog thresholds are employed
by enabling the corresponding bit of the alternate watchdog input bus.
An example of the operation is shown in Table 34-44 .
34.4.6 DMA Functionality
A Direct Memory Access (DMA) request can be programmed after the conversion of every channel by
setting the respective masking bit in DMAR
n registers. The DMA masking registers must be programmed
before starting any conversion.
DMA interface signals timings are described in Figure 34-51 .
DMA transfers can be enabled by setting the DMAE[DMAEN] bit. When DMAE[DCLR] is set then the
DMA request is cleared on the reading of the register for which DMA transfer has been enabled.
Table 34-44. Example for ad_awpwm_o Operation
Converted data
watchdog(n)
Upper Threshold
watchdog(n)
Lower Threshold
watchdog(n)
THRINV
watchdog(n)
AD_AWPWM(n)
0x0155 0x0055 0x0000 0 0
0x0055 0x01FF 0x0088 0 1
0x0155 0x0055 0x0000 1 1
0x0055 0x01FF 0x0088 1 0