NXP Semiconductors PXN2020, Reference Manual, Page: 431 / 1376

AMBA Crossbar Switch (AXBS)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 16-5
NOTE
Masters must be assigned unique priority levels.
The master priority register can only be accessed in supervisor mode with 32-bit accesses. After the read
only (RO) bit is set in the slave general-purpose control register, the master priority register can only be
read. Attempts to write to it have no effect on the MPR and result in an error.
NOTE
XBAR_MPR must be written with a read/modify/write for code
compatibility.
Address: AXB 0x0000 (XBAR_MPR0)
AXB 0x0100 (XBAR_MPR1)
AXB 0x0200 (XBAR_MPR2)
AXB 0x0300 (XBAR_MPR3)
AXB 0x0600 (XBAR_MPR6)
AXB 0x0700 (XBAR_MPR7)
Access: Supervisor read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
MSTR7
0
MSTR6
0 0 0 0 0 0 0 0
W
Reset 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0
MSTR3
0
MSTR2
0
MSTR1
0
MSTR0
W
Reset 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0
Figure 16-2. Master Priority Registers (XBAR_MPRn)
Table 16-4. XBAR_MPRn Descriptions
Field Description
MSTR7 Master 7 priority. Set the arbitration priority for master port 6 on the associated slave port.
000 This master has the highest priority when accessing the slave port.
101 This master has the lowest priority when accessing the slave port.
110–111
Invalid values
MSTR6 Master 6 priority. Set the arbitration priority for master port 6 on the associated slave port.
000 This master has the highest priority when accessing the slave port.
101 This master has the lowest priority when accessing the slave port.
110–111
Invalid values
MSTR3 Master 3 priority. Set the arbitration priority for master port 3 on the associated slave port.
000 This master has the highest priority when accessing the slave port.
101 This master has the lowest priority when accessing the slave port.
110–111
Invalid values
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