NXP Semiconductors PXN2020, Reference Manual, Page: 306 / 1376

Interrupts and Interrupt Controller (INTC)
PXN20 Microcontroller Reference Manual, Rev. 1
10-38 Freescale Semiconductor
Figure 10-21. Hardware Vector Mode Handshaking Timing Diagram
10.5 Initialization/Application Information
10.5.1 Initialization Flow
After exiting reset, all of the PRI n and PRC_SEL n fields in the INTC priority select registers
(INTC_PSR0–INTC_PSR315) are cleared (set to 0), and PRI in both INTC_CPR_PRC0 and
INTC_CPR_PRC1 is set to 0xF (0b1111). These reset values prevent the INTC from asserting interrupt
requests to the processors. The enable or mask bits in the peripherals are reset such that the peripheral
interrupt requests are negated.
An initialization sequence for allowing the peripheral and software settable interrupt requests to cause an
interrupt request to the processor is:
interrupt_request_initialization:
configure VTES_PRC0,VTES_PRC1,HVEN_PRC0 and HVEN_PRC1 in INTC_MCR
configure VTBA_PRC n in INTC_IACKR_PRC n
raise the PRI n fields and set the PRC_SEL x fields to the desired processor in INTC_PSR n _ n
set the enable bits or clear the mask bits for the peripheral interrupt requests
lower PRI in INTC_CPR_PRC n to zero
enable processor(s) recognition of interrupts
10.5.2 Interrupt Exception Handler
These example interrupt exception handlers use Power Architecture assembly code.
Clock
Interrupt Request
to Processor
Hardware Vector
Enable
Interrupt
Acknowledge
Interrupt Vector
Read
INTC_IACKR_PCRn
Write
INTC_EOIR_PCRn
INTVEC in
INTC_IACKR_PCRn
PRI in
INTC_CPR_PCRn
Peripheral Interrupt
Request 100
0
0 108
0
108
0 1