NXP Semiconductors PXN2020, Reference Manual, Page: 381 / 1376

e200z6 Core (Z6)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 13-17
example, program code might be execute-only and data structures can be mapped as
read/write/no-execute.
The UX, SX, UW, SW, UR, and SR access control bits support selective permissions for access control:
• SR—Supervisor read permission. Allows loads and load-type cache management instructions to
access the page while in supervisor mode.
• SW—Supervisor write permission. Allows stores and store-type cache management instructions to
access the page while in supervisor mode.
• SX—Supervisor execute permission. Allows instruction fetches to access the page and instructions
to be executed from the page while in supervisor mode.
• UR—User read permission. Allows loads and load-type cache management instructions to access
the page while in user mode.
• UW—User write permission. Allows stores and store-type cache management instructions to
access the page while in user mode.
• UX—User execute permission. Allows instruction fetches to access the page and instructions to be
executed from the page while in user mode.
If the translation match was successful, the permission bits are checked as shown in Figure 13-6 . If the
access is not allowed by the access permission mechanism, the processor generates an instruction or data
storage interrupt (ISI or DSI).
Figure 13-6. Granting of Access Permission
13.3.1.5 MMU Assist Registers (MAS[0:4], MAS[6])
The e200z6 uses six special purpose registers (MAS[0], MAS[1], MAS[2], MAS[3], MAS[4], and
MAS[6]) to facilitate reading, writing, and searching the TLBs. The MAS registers can be read or written
using the
mfspr and mtspr instructions. The e200z6 does not implement the MAS5 register, present in
other Freescale EIS designs, because the tlbsx instruction only searches based on a single SPID value.
For more information on the MAS n registers is available in the e200z6 PowerPC
TM
Core Reference
Manual .
Access Granted
Instruction Fetch
MSR[PR]
TLB_entry[UX]
TLB_entry[SX]
Load-class Data Access
TLB_entry[UR]
TLB_entry[SR]
Store-class Data Access
TLB_entry[UW]
TLB_entry[SW]
TLB