NXP Semiconductors PXN2020, Reference Manual, Page: 332 / 1376

Flash Memory Array and Control
PXN20 Microcontroller Reference Manual, Rev. 1
12-6 Freescale Semiconductor
12.3.2 Register Descriptions
This section lists the flash memory registers in address order and describes the registers and their bit fields.
12.3.2.1 Module Configuration Register (MCR)
The MCR register is shown in Figure 12-3 and Table 12-3 .
0x0028 PFSACC—Platform flash supervisor access control
register R/W
1
0x00FF_FE08 12.3.2.10/12-21
0x002C PFDACC—Platform flash data access control register R/W
1
0x00FF_FE10 12.3.2.11/12-23
0x0030 – 0x0038 Reserved
0x003C UT0—UTest register 0 R/W
1
0x0000_0001 12.3.2.12/12-23
0x0040 UT0—UTest register 1 R/W 0x0000_0000 12.3.2.13/12-25
0x0044 UT0—UTest register 2 R/W 0x0000_0000 12.3.2.14/12-26
0x0048 UM0—User multiple input signature register 0 R/W 0x0000_0000 12.3.2.15/12-26
0x004C UM1—User multiple input signature register 1 R/W 0x0000_0000 12.3.2.15/12-26
0x0050 UM2—User multiple input signature register 2 R/W 0x0000_0000 12.3.2.15/12-26
0x0054 UM3—User multiple input signature register 3 R/W 0x0000_0000 12.3.2.15/12-26
0x0058 UM4—User multiple input signature register 4 R/W 0x0000_0000 12.3.2.15/12-26
0x0048 – 0x3FFF Reserved
1
Some bits are read-only.
Offset: FLASH_REG 0x0000 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 SIZE 0 LAS 0 0 0 MAS
W
Reset 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R EER RWE SBC 0 PEAS DONE PEG 0 0 0 0
PGM PSUS ERS ESUS EHV
W w1c w1c w1c
Reset 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0
Figure 12-3. Module Configuration Register (MCR)
Table 12-2. Flash Configuration Register Memory Map (continued)
Offset from
FLASH_REGS_BASE
(0xFFFF_8000)
Register Access Reset Value Section/Page