NXP Semiconductors PXN2020, Reference Manual, Page: 349 / 1376

Flash Memory Array and Control
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 12-23
12.3.2.11 PFlash Data Access Control Register (PFDACC)
12.3.2.12 User Test Register 0 (UT0)
The User Test Register 0 (UT0) provides a means to control UTest. The UTest mode gives the users of the
flash module the ability to perform test features on the flash. This register is only writable when the flash
is put into UTest mode by writing a passcode.
xACC[28] 0x34_0000 256 KB
xACC[29] 0x38_0000 256 KB
xACC[30] 0x3C_0000 256 KB
xACC[31] Reserved
Offset: FLASH_REG 0x002C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
DACC[30:16]
W
Reset 0 0 — — 1 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
DACC[15:0]
W
Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Figure 12-13. PFlash Data Access Control Register (PFSACC)
Table 12-15. PFlash Data Access Control Register (PFDACC) Field Descriptions
Field Description
DACC[31:0]
Data Access Control. This bit field defines code/data access control for each sector within the main flash
array.
0 Flash array sector n can be accessed only by a data reference. An attempted instruction fetch is terminated
with an AHB error response. If the requesting bus master is the processor core, the ERROR response
typically generates an instruction abort or data abort exception.
1 Flash array sector n can be accessed either as an instruction or data reference.
The mapping of this bit field to the main flash array is defined in
Table 12-14 .
This field is initialized by hardware reset to the value contained in address 0x3E10 of the shadow block of the
flash array. An erased or unprogrammed flash sets this field to 0xFFFF_FFFF.
Table 12-14. {S,D}ACC Register to Flash Array Mapping
Register Bit
Starting Flash
Array Address
Sector Size