NXP Semiconductors PXN2020, Reference Manual, Page: 419 / 1376

Semaphores
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 15-7
watchdog timer, the secure gate reset requires two consecutive writes with predefined data patterns from
the same processor to force the clearing of the specified gate(s). The required access pattern is:
1. A processor performs a 16-bit write to the SEMA4_RSTGT memory location. The most significant
byte (SEMA4_RSTGT[RSTGDP]) must be 0xE2; the least significant byte is a “don’t care” for this
reference.
2. The same processor then performs a second 16-bit write to the SEMA4_RSTGT location. For this
write, the upper byte (SEMA4_RSTGT[RSTGDP]) is the logical complement of the first data
pattern (0x1D) and the lower byte (SEMA4_RSTGT[RSTGTN]) specifies the gate(s) to be reset.
This gate field can specify a single gate be cleared or that all gates are cleared.
3. Reads of the SEMA4_RSTGT location return information on the 2-bit state machine
(SEMA4_RSTGT[RSTGSM]) which implements this function, the bus master performing the
reset (SEMA4_RSTGT[RSTGMS]) and the gate number(s) last cleared
(SEMA4_RSTGT[RSTGTN]). Reads of the SEMA4_RSTGT register do not affect the secure reset
finite state machine in any manner.
Figure 15-5. Semaphores (Secure) Reset Gate n (SEMA4_RSTGT)
Offset: SEMA 0x0100 (SEMA4_RSTGT) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 RSTGSM 0 RSTGMS
RSTGTN
W RSTGDP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0