NXP Semiconductors PXN2020, Reference Manual, Page: 1053 / 1376

Inter-Integrated Circuit Bus Controller Module (I
2
C)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 32-9
32.3.2.4 I
2
C Bus Status Register (IBSR)
RSTA Repeat Start. Writing a 1 to this bit generates a repeated START condition on the bus, provided it is the current bus
master. This bit is always read as a low. Attempting a repeated start at the wrong time, if the bus is owned by another
master, results in loss of arbitration.
0 No effect.
1 Generate repeat start cycle.
DMAEN DMA enable. When this bit is set, the DMA TX and RX lines are asserted when the I
2
C module requires data to be
read or written to the data register. No transfer done interrupts are generated when this bit is set; however, an
interrupt is generated if loss of arbitration or addressed as slave conditions occur. The DMA mode is valid only when
the I
2
C module is configured as a master and the DMA transfer still requires CPU intervention at the start and the
end of each frame of data. See the DMA application information section for more details.
0 Disable the DMA TX/RX request signals.
1 Enable the DMA TX/RX request signals.
Offset: 0x0003 Access: User read/write
0 1 2 3 4 5 6 7
R TCF IAAS IBB
IBAL
0 SRW IBIF RXAK
W w1c
Reset 1 0 0 0 0 0 0 0
Figure 32-7. I
2
C Bus Status Register (IBSR)
Table 32-6. IBSR Field Descriptions
Field Description
TCF Transfer Complete. While one byte of data is transferred, this bit is cleared. It is set by the falling edge of the ninth
clock of a byte transfer. This bit is valid only during or immediately following a transfer to the I
2
C module or from the
I
2
C module.
0 Transfer in progress.
1 Transfer complete.
IAAS Addressed as a Slave. When its own specific address (I-bus address register) is matched with the calling address,
this bit is set. The CPU is interrupted provided the IBIE is set. Then the CPU must check the SRW bit and set its
Tx/Rx mode accordingly. Writing to the I-bus control register clears this bit.
0 Not addressed.
1 Addressed as a slave.
IBB Bus Busy. This bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a STOP signal
is detected, IBB is cleared and the bus enters idle state.
0 Bus is idle.
1 Bus is busy.
IBAL Arbitration Lost. The arbitration lost bit (IBAL) is set by hardware when the arbitration procedure is lost. Arbitration
is lost in the following circumstances:
• SDA is sampled low when the master drives a high during an address or data transmit cycle.
• SDA is sampled low when the master drives a high during the acknowledge bit of a data receive cycle.
• A start cycle is attempted when the bus is busy.
• A repeated start cycle is requested in slave mode.
• A stop condition is detected when the master did not request it.
This bit must be cleared by software, by writing a one to it. A write of zero has no effect.
Table 32-5. IBCR Field Descriptions (continued)
Field Description