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Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
36-7
Refer to
Chapter 3, Signal Description,
for detailed signal descriptions.
36.4
Memory Map and Registers
The NDI block contains no memory mapped registers. Nexus registers are accessed by the development
tool via the JTAG port using a client select and a register index. The client select is controlled by loading
the correct access instruction into the JTAG controller, as described in
Section 35.4.4, JTAGC Instructions.
After the desired client TAP is selected, OnCE registers for that client are accessible by loading the
appropriate value in the RS[0:6] field of the OnCE command register (OCMD), as described in
Section 35.5.3.1, OnCE Command Register (OCMD).
Nexus is enabled, and the associated Nexus
registers become accessible, by loading the NEXUS_ENABLE instruction into the RS[0:6] field of the
OCMD. When Nexus register access is enabled, the desired Nexus register is accessible using the index
shown in
.
Detailed sequences for register access are described in
Section 36.6.10.8, IEEE 1149.1 (JTAG)
. Detailed sequences for register access are described in
IEEE 1149.1 (JTAG) RD/WR Sequences
JCOMP
JTAG
JTAG Compliancy and TAP Sharing Control
TCK
JTAG
Test Clock Input
TDI
JTAG
Test Data Input
TDO
JTAG
Test Data Output
TMS
JTAG
Test Mode Select Input
Table 36-2. Nexus Client JTAG Instructions
Instruction
Description
Opcode
NPC JTAG Instruction Opcodes
NEXUS_ENABLE
Opcode for NPC Nexus Enable instruction (4-bits)
0x0
BYPASS
Opcode for the NPC BYPASS instruction (4-bits)
0xF
e200z6 OnCE JTAG Instruction Opcodes
1
1
Refer to the e200z6 Reference Manual for a complete list of available OnCE instructions.
NEXUS3_ACCESS
Opcode for e200z6 OnCE Nexus Enable instruction (10-bits)
0x7C
BYPASS
Opcode for the e200z6 OnCE BYPASS instruction (10-bits)
0x7F
e200z0 OnCE JTAG Instruction Opcodes
2
2
Refer to the e200z0 Reference Manual for a complete list of available OnCE instructions.
NEXUS2_ACCESS
Opcode for e200z0 OnCE Nexus Enable instruction (10-bits)
0x7C
BYPASS
Opcode for the e200z0 OnCE BYPASS instruction (10-bits)
0x7F
Table 36-1. Signal Properties (continued)
Name
Port
Function
Summary of Contents for PXN2020
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