NXP Semiconductors PXN2020, Reference Manual, Page: 284 / 1376

Interrupts and Interrupt Controller (INTC)
PXN20 Microcontroller Reference Manual, Rev. 1
10-16 Freescale Semiconductor
The software set/clear interrupt registers support the setting or clearing of software settable interrupt
request. These registers contain eight independent sets of bits to set and clear a corresponding flag bit by
software. Excepting being set by software, this flag bit behaves the same as a flag bit set within a
peripheral. This flag bit generates an interrupt request within the INTC like a peripheral interrupt request.
Writing a 1 to SET
n leaves SET n unchanged at 0 but sets CLR n . Writing a 0 to SET n has no effect. CLR n
is the flag bit. Writing a 1 to CLR n clears it. Writing a 0 to CLR n has no effect. If a 1 is written
simultaneously to a pair of SET n and CLR n bits, CLR n is asserted, regardless of whether CLR n was
asserted before the write.
10.3.2.9 INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR312_315)
Table 10-8. INTC_SSCIR[0:7] Field Descriptions
Field Description
SET Set Flag Bits. Writing a 1 sets the corresponding CLRn bit. Writing a 0 has no effect. Each SETn is always
read as a 0.
CLR Clear Flag Bits. CLRn is the flag bit. Writing a 1 to CLRnx clears it provided that a 1 is not written
simultaneously to its corresponding SETn bit. Writing a 0 to CLRn has no effect.
0 Interrupt request not pending within INTC.
1 Interrupt request pending within INTC.
Offset: INTC_BAS 0x0040 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
PRC_SEL0
0 0
PRI0 PRC_SEL1
0 0
PRI1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
PRC_SEL2
0 0
PRI2 PRC_SEL3
0 0
PRI3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 10-18. INTC Priority Select Register 0–3 (INTC_PSR0–3)
Offset: INTC_BAS 0x0178 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
PRC_
SEL312
0 0
PRI312
PRC_
SEL313
0 0
PRI313
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
PRC_
SEL314
0 0
PRI314
PRC_
SEL315
0 0
PRI315
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 10-19. INTC Priority Select Register 312–315 (INTC_PSR312–315)