NXP Semiconductors PXN2020, Reference Manual, Page: 1229 / 1376

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 36-79
Table 36-53 details the status bit encodings.
Nexus Reg: 0x7 Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
AC RW SZ MAP PR BST
0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CNT ERR DV
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 36-56. Read/Write Access Control/Status Register (RWCS)
Table 36-52. RWCS Field Description
Field Description
AC Access control.
0 End access
1 Start access
RW Read/write select.
0 Read access
1 Write access
SZ[2:0] Word size.
000 8-bit (byte)
001 16-bit (half-word)
010 32-bit (word)
011 Reserved
100–111 Reserved (default to word)
MAP[2:0] MAP select.
000 Primary memory map
001-111 Reserved
PR[1:0] Read/write access priority.
00 Lowest access priority
01 Reserved (default to lowest priority)
10 Reserved (default to lowest priority)
11 Highest access priority
BST Burst control.
0 Module accesses are single bus cycle at a time.
1 Module accesses are performed as burst operation.
CNT[13:0] Access control count. Number of accesses of word size SZ
ERR Read/write access error. See Table 36-53 .
DV Read/write access data valid. See Table 36-53 .