NXP Semiconductors PXN2020, Reference Manual, Page: 1026 / 1376

Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
31-36 Freescale Semiconductor
Figure 31-31. DMA-Controlled SCI Data Frame Reception
31.4.5.3.11 Receiver Overrun
When the eSCI module has received a frame and attempts to transfer the payload data of the received frame
into the eSCI SCI Data Register (eSCI_SDR) but neither the application nor the DMA controller has read
the eSCI SCI Data Register (eSCI_SDR) since its last update, the overrun flag OR in the eSCI Interrupt
Flag and Status Register 1 (eSCI_IFSR1) is set. The data contained in eSCI SCI Data Register
(eSCI_SDR) are not changed and the received data are lost.
31.4.5.3.12 Wake-up Frame Reception
This section describes the reception process when the receiver is in the wakeup state.
When the required number of frame bits have been received, the payload bits of the received frame are
transferred into eSCI SCI Data Register (eSCI_SDR) if the RDRF flag is 0.
If the address-mark wake-up mode is selected and the received frame has the address bit set, the receive
data register full flag RDRF in eSCI Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set. If the receive
interrupt enable bit RIE in the eSCI Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set, the RDRF
interrupt request is generated. The RWU bit is cleared, and the receiver enters the run state via the wake1
transition.
If the idle line wake-up mode is selected and the receiver has detected an idle character, The RWU bit is
cleared, and the receiver enters the ready state via the wake0 transition.
If any of the receiver errors described in Section 31.4.5.4, Reception Error Reporting, have been occurred,
that corresponding flags are set.
31.4.5.3.13 Bit Sampling
The receiver samples the selected receiver input (see Section 31.4.5.3.2, Receiver Input Mode Selection )
with the receiver clock RCLK. The sampling for start bit detection is shown in Figure 31-32 . The sampling
for data and stop bit reception is shown in Figure 31-33 . The samples indicated by dashed arrows are not
DMA
Controller
eSCI
System Memory
DATA 1 DATA n
SCI data frame
RX DMA
channel
DATA 2
DATA n
DATA 1