NXP Semiconductors PXN2020, Reference Manual, Page: 1170 / 1376

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
36-20 Freescale Semiconductor
Figure 36-10. Transmission Sequence of Messages
Detailed message descriptions for the module are described in Section 36.6.10. Detailed message
descriptions for the module are described in Section 36.7.9.
36.5.5.2.3 NPC IEEE 1149.1-2001 (JTAG) TAP
The NPC uses the IEEE

1149.1-2001 TAP, which uses the state machine shown in Figure 35-6 for
accessing registers. The NPC also implements the Nexus controller state machine as defined by the
IEEE-ISTO 5001-2003 standard as shown in
Figure 36-11 .
The instructions implemented by the NPC TAP controller are listed in Table 36-2 .
Enabling the NPC TAP Controller
Assertion of the power-on reset signal, or negating JCOMP resets the NPC TAP controller. When not in
power-on reset, the NPC TAP controller is enabled by asserting JCOMP and loading the
ACCESS_AUX_TAP_NPC instruction in the JTAGC. Loading the NEXUS-ENABLE instruction then
grants access to NPC registers.
Retrieving Device IDCODE
The Nexus TAP controller does not implement the IDCODE instruction. However, the device
identification message can be output by the NPC through the auxiliary output port or shifted out serially
by accessing the NPC device ID register through the TAP. If the NPC is enabled, transmission of the device
identification message on the auxiliary output port MDO pins occurs immediately after a write to the PCR.
Transmission of the device identification message serially through TDO is achieved by performing a read
of the register contents.
Loading NEXUS-ENABLE Instruction
Access to the NPC registers is enabled by loading the NPC NEXUS-ENABLE instruction when NPC has
ownership of the TAP. This instruction is shifted in via the SELECT-IR-SCAN path and loaded in the
UPDATE-IR state. At this point, the Nexus controller state machine, shown in
Figure 36-11 , transitions to
the REG_SELECT state. The Nexus controller has three states: idle, register select, and data access.
Table 36-11 illustrates the IEEE

1149.1 sequence to load the NEXUS-ENABLE instruction.
FIELD #3
MSB LSB
1 2 3
FIELD #2 FIELD #1 TCODE
4
6 bits