NXP Semiconductors PXN2020, Reference Manual, Page: 133 / 1376

PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 6-1
Chapter 6
Clocks, Reset, and Power (CRP)
6.1 Introduction
The primary function of the clock, reset, and power (CRP) block is to maintain all of the control logic that
requires power when other portions of the device are powered down in power-saving modes. The CRP
manages entry into, operation during, and exit from power-saving modes.
The CRP consists of the input isolation block, the RTC/API, the wakeup and power status block, the clock
and reset control block, low-power state machine, and bus interface unit. The input isolation block allows
inputs from external blocks to be driven to known states when the logic driving the input is powered down.
The RTC/API block implements a real-time counter and periodic interrupt. The wakeup and power status
block implements the logic to select power mode operation and wakeup sources. The clock and reset
control block implements miscellaneous logic related to PLL and oscillator operation, and reset gating for
power-saving modes. The low-power state machine controls the transitions into and out of the power-
saving modes. The bus interface unit allows for slave read/write register access from the device’s core.
There are also several miscellaneous integration functions included in the CRP that are discussed in detail
in later sections of this chapter.
6.1.1 Block Diagram
A simplified block diagram of the CRP illustrates the functionality and interdependence of major blocks
(see
Figure 6-1 ).