NXP Semiconductors PXN2020, Reference Manual, Page: 208 / 1376

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
8-26 Freescale Semiconductor
Section 8.3.2.13.3, Pad Configuration Registers 144–146 (SIU_PCR144–SIU_PCR146). For each pin,
Table 3-1 lists the signals that are available as the PA settings for Function1, Function2, and Function3.
See Table 8-16 for bit field definitions.
8.3.2.13.3 Pad Configuration Registers 144–146 (SIU_PCR144–SIU_PCR146)
The SIU_PCR144 to SIU_PCR146 registers control the pin function, direction, and static electrical
attributes of the Port K pins 0–2 (PK0–PK2). For each pin,
Table 3-1 lists the signals that are available as
the PA settings for Function1, Function2, and Function3.
See Table 8-16 for bit field definitions.
8.3.2.14 GPIO Pin Data Output Registers (SIU_GPDO16_19–SIU_GPDO152_154)
The SIU_GPDO16_19 register definition is in Figure 8-17 . All other SIU_GPDO n registers follow the
same pattern where four GPDO bits are placed in a 32-bit word, with one bit per byte. Each of the 139
PDO bits corresponds to a port pin in the order given in
Table 8-18 . Gaps exist in this memory space where
the pin is not available in the package.
NOTE
On PXN20, the Port A pins are only general-purpose inputs. Therefore,
there are no output data registers associated with these pins.
The SIU_GPDO n registers are written to by software to drive data out on the external GPIO pin. Each byte
of a register drives a single external GPIO pin, which allows the pin state to be controlled independently
from other GPIO pins. Writes to the SIU_GPDO
n registers do not affect pin states if the pins are
configured as inputs or as non-GPIO function by the associated pad configuration registers. The
SIU_GPDO
n register values are automatically driven to the GPIO pins without software update if the
GPIO pins’ direction changes from input to output.
Offset: S0x0060–S0x015E; S0x0166–S0x0174 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE IBE
0 0
ODE HYS SRC WPE WPS
W
Reset 0 0 0 0 0 0 0 U
1
0 0 0 0 0 0 0
1
0
1
The reset value is 1 for SIU_PCR153 (BOOTCFG), 0 for all other SIU_PCRs in this range.
Figure 8-15. Port B to Port K Pad Config Registers (SIU_PCR16–SIU_PCR143, SIU_PCR147–SIU_PCR154)
Offset: S0x0160–S0x0164 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE IBE DSC
1
ODE HYS
0 0
WPE WPS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
When using PK[0:2] for MLB (PA = 0b01), the recommended value for DSC is 0b11.
Figure 8-16. Port K[0:2] Pad Configuration Registers (SIU_PCR144–SIU_PCR146)