NXP Semiconductors PXN2020, Reference Manual, Page: 201 / 1376

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 8-19
8.3.2.7 Overrun Status Register (SIU_OSR)
The SIU_OSR contains flag bits that record an overrun. These flag bits are cleared by writing 1 to the bits
(w1c); writing 0 has no effect.
8.3.2.8 Overrun Request Enable Register (SIU_ORER)
The SIU_ORER contains bits to enable an overrun if the corresponding flag bit is set in the SIU_OSR. If
any overrun request enable bit and the corresponding flag bit are set, the single combined overrun request
from the SIU to the interrupt controller is asserted.
Offset: SI 0x0020 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R OVF
15
OVF
14
OVF
13
OVF
12
OVF
11
OVF
10
OVF
9
OVF
8
OVF
7
OVF
6
OVF
5
OVF
4
OVF
3
OVF
2
OVF
1
OVF
0
W
Reset w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Figure 8-8. Overrun Status Register (SIU_OSR)
Table 8-10. SIU_OSR Field Descriptions
Field Function
OVFn Overrun Flag n. This bit is set when an overrun occurs on the corresponding IRQn pin.
0 No overrun occurred on the corresponding IRQn pin.
1 An overrun occurred on the corresponding IRQn pin.
Offset: SI 0x0024 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R ORE
15
ORE
14
ORE
13
ORE
12
ORE
11
ORE
10
ORE
9
ORE
8
ORE
7
ORE
6
ORE
5
ORE
4
ORE
3
ORE
2
ORE
1
ORE
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-9. Overrun Request Enable Register (SIU_ORER)