Renesas Hitachi H8S/2191, Hardware Manual

Page: 741 / 1065

Rev. 2.0, 11/00, page 714 of 1037
(2) Capstan Phase Error Data Registers (CPER1, CPER2)
0
0
1
0
R
*
/W
2
0
R
*
/W
3
0
4
1
5
1
6
1
7
— — — —
— — — —
R
*
/W R
*
/W
1
Bit :
Initial value :
R/W :
0
R
*
/W
13
0
R
*
/W
14
0
R
*
/W
15 1 0 3 2 5 4 7
0
R
*
/W
6
0
R
*
/W
9
0
R
*
/W
8
0
R
*
/W
11
0
R
*
/W
10
0
R
*
/W
0
R
*
/W R
*
/W R
*
/W R
*
/W R
*
/W R
*
/W R
*
/W
12
0 0 0 0 0 0
Bit :
Initial value :
R/W :
Note:
*
Note that only detected error data can be read.
CPER1 and CPER2 constitute a 20-bit capstan phase error data register. The 20 bits are
weighted as follows. Bit 3 of CPER1 is the MSB. Bit 0 of CPER2 is the LSB. When the
rotational phase is correct, the data H'00000 is latched. Negative data will be latched if the
phase leads the correct phase, and positive data if it lags. Values in CPER1 and CPER 2 are
transferred to the digital filter circuit.
CPER1 and CPER are 20-bit readable/writable registers. When writing data to CPER1 and
CPER2, write to CPER1 first, and then write to CPER2. CPER2 is accessible by word access
only. Byte access gives unassured results. CPER1 and CPER2 are initialized to H'F0 and
H'0000 by a reset, and in standby mode.
See the note on the capstan phase preset data registers (CPPR1 and CPPR2) in section 28.9.4 (1).