Renesas Hitachi H8S/2191, Hardware Manual, Page: 923 / 1065

Rev. 2.0, 11/00, page 896 of 1037
A.5 Bus Status During Instruction Execution
Table A.6 indicates execution status of each instruction available in this LSI. For the number of
states required for each execution status, see table A.4, Number of States Required for Each
Execution Status (Cycle).
[How to see the table]
Instruction
JMP@aa:24 R:W 2nd
Internal operation
1 state
R:W EA
1 2 3 4 5 6 7 8
End of instruction
Order of execution
Effective address is read by word.
Read/write not executed
The 2nd word of the instruction currently being
executed is read by word.
[Legend]
R : B Read by byte
R : W Read by word
W : B Write by byte
W : W Write by word
: M Bus not transferred immediately after this cycle
2nd Address of the 2nd word (3rd and 4th bytes)
3rd Address of the 3rd word (5th and 6th bytes)
4th Address of the 4th word (7th and 8th bytes)
5th Address of the 5th word (9th and 10th bytes)
NEXT The head address of the instruction immediately after the instruction
currently being executed
EA Execution address
VEC Vector address