Renesas Hitachi H8S/2191, Hardware Manual, Page: 715 / 1065

Rev. 2.0, 11/00, page 688 of 1037
Bit 2: Drum Phase System Filter Computation Automatic Start Bit (DPCNT)
Sets on the filter computation of the phase system if an underflow occurred in the drum lock
counter.
Bit 2
DPCNT Description
0 Does not perform the filter computation by detection of the drum lock (Initial value)
1 Sets on the filter computation of the phase system when drum lock is detected
Bits 1 and 0: Drum Lock Counter Setting Bits (DFRCS1, DFRCS0)
Set the number of times where drum lock has been determined (DFG has been detected in the
range set by the lock range data register). It sets the drum lock flag if it detected the set number
of times of occurrence of drum lock. If an NCDFG signal is detected outside the lock range
after data is written in DFRCS1 and 0, data is stored in the lock counter.
Note: If DFRCS1 or DFRCS0 is read-accessed, the counter value is read out. If bit 3 (drum
lock flag) is 1 and the drum lock counter's value is 3, it indicates that the drum speed
system is locked. The drum look counter stops until lock is released after underflow.
Bit 1 Bit 0
DFRCS1 DFRCS0 Description
0 Underflow after lock was detected once (Initial value) 0
1 Underflow after lock was detected twice
0 Underflow after lock was detected three times 1
1 Underflow after lock was detected four times