Renesas Hitachi H8S/2191, Hardware Manual

Page: 534 / 1065

Rev. 2.0, 11/00, page 507 of 1037
Bit 0: Start Flag (STF)
The STF controls the start of transfer operations. When this bit is set to 1 and PMR30 of PMR3
is 0, transfer operation of the SCI2 is started. When PMR30 of PMR3 is 1, the low level of the
&6 pin is detected and transfer is started. This bit retains 1 during transfer and in the &6 input
standby mode, and it is cleared to 0 after completion of transfer and when transfer is cut off by
the
&6 pin. Therefore, this bit can be used as a busy flag. When this bit is cleared to 0 during
transfer, the transfer is cut off and the SCI2 is initialized. At this time the contents of internal
registers other than the SCR2 and the serial data buffer (32 bytes) are retained.
Bit 0
STF Description
Read Transfer operations stops (Initial value) 0
Write Transfer operation discontinues and the SCI2 is initialized
Read During transfer operation or in
&6
input standby mode 1
Write Transfer operation starts
24.2.5 Module Stop Control Register (MSTPCR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Bit :
Initial value :
R/W :
The MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode
control. When the MSTPCR is set to 1, the SCI2 stops at the end of bus cycle and a transition is
made to the module stop mode. For details, see section 4.5 Module Stop Mode.
The MSTPCR is initialized to H'FFFF by a reset.
Bit 7: Module Stop (MSTP7)
Specifies the SCI2 module stop mode.
MSTPCRL
Bit 7
MSTP7 Description
0 SCI2 module stop mode is cleared
1 SCI2 module stop mode is set (Initial value)