Renesas Hitachi H8S/2191, Hardware Manual

Page: 117 / 1065

Rev. 2.0, 11/00, page 90 of 1037
5.2 Reset
5.2.1 Overview
A reset has the highest exception priority.
When the
5(6 pin goes low, all processing halts and the MCU enters the reset state. A reset
initializes the internal state of the CPU and the registers of on-chip supporting modules.
Immediately after a reset, interrupt control mode 0 is set.
Reset exception handling begins when the
5(6 pin changes from low to high.
The MCUs can also be reset by overflow of the watchdog timer. For details, see section 17,
Watchdog Timer.
5.2.2 Reset Sequence
The MCU enters the reset state when the
5(6 pin goes low.
To ensure that the chip is reset, hold the
5(6 pin low during the oscillation stabilizing time of
the clock oscillator when powering on. To reset the chip during operation, hold the
5(6 pin low
for at least 20 states. For pin states in a reset, see Appendix D.1, Pin Circuit Diagrams.
When the
5(6 pin goes high after being held low for the necessary time, the chip starts reset
exception handling as follows:
[1] The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit is set to 1 in CCR.
[2] The reset exception vector address is read and transferred to the PC, and program execution
starts from the address indicated by the PC.
Figures 5.2 shows examples of the reset sequence.